HY63V8100A Series
128Kx8bit CMOS FAST SRAM
PRELIMINARY
DESCRIPTION
The HY63V8100A is a 1,048,576-bit high-speed,
SRAM organized as 131,072 words by 8-bits. The
HY63V8100A uses eight common input and output
lines and has an output enable pin which operates
faster than. address access time at read cycle. The
device is fabricated using Hyundai's advanced
CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in
high-density high-speed system applications
FEATURES
•
•
•
•
Single 3.3V
±
0.3V Power Supply
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Low data Retention Voltage:
- 2.0V(min) – L-ver. Only
•
Center Power/Ground Pin Configuration
•
Standard pin configuration
- 32pin 400mil SOJ/TSOP-ll
Product
No.
HY63V8100A
HY63V8100A
HY63V8100A
Supply
Voltage(V)
3.3
3.3
3.3
Speed
(ns)
8
10
12
Operation
Current(mA)
200
190
180
Standby Current(mA)
L
5
5
5
0.5
0.5
0.5
PIN CONNECTION
A0
BLOCK DIAGRAM
ROW
DECODER
SENSE AMP
I/O1
OUTPUT BUFFER
I/O8
A0
A1
A2
A3
/CS
I/O1
I/O2
Vcc
Vss
I/O3
I/O4
/WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SOJ/
TSOP2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
/OE
I/O8
I/O7
Vss
Vcc
I/O6
I/O5
A12
A11
A10
A9
A8
ADD INPUT BUFFER
DECODER
MEMORY ARRAY
512x256x8
A16
/CS
/OE
SOJ/TSOP2
/WE
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
I/O1~I/O8
Pin Function
Chip Select
Write Enable
Output Enable
Data Inputs/Outputs
Pin Name
A0~A16
Vcc
Vss
N.C
Pin Function
Address Input
Power(+3.3V)
Ground
No Connection
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.02 / Jan.99
Hyundai Semiconductor
WRITE DRIVER
HY63V8100A Series
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
V
IN,
V
OUT
Vcc
T
A
T
STG
P
D
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc Supply Relative to Vss
Commercial
Operating Temperature
Industrial
Storage Temperature
Power Dissipation
Rating
-0.5 to 4.6
-0.5 to 5.5
0 to 70
-40 to 85
-65 to 150
1.0
Unit
V
V
°C
°C
°C
W
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0°C to 70°C)
Symbol
Vcc
Vss
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3(1)
Type
3.3
0
-
-
Max.
3.6
0
Vcc+0.3(2)
0.8
Unit
V
V
V
V
Note
1. V
IL (min)
= -2.0V a.c(pulse width less than 8ns) for I
<
20mA
2. V
IH
(max) = Vcc + 2.0V a.c(pulse width less than 8ns) for I
<
20mA
DC ELECTRICAL CHARACTERISTICS
(Vcc = 3.3V±0.3V, T
A
= 0°C to 70°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Input Leakage Current
I
LI
V
SS
<
V
IN
<
V
CC
Output Leakage Current V
SS
<
V
OUT
<
V
CC
,
I
LO
/CS = V
IH
or
/
OE
=
V
IH
or /WE = V
IL
/CS = V
IL
, V
IN =
V
IH
,
8ns
I
CC
Operating Current
I
I/O
= 0mA
10ns
Min. Duty Cycle = 100%
12ns
TTL Standby Current
/CS = V
IH,
V
IN=
V
IH
or V
IL
Min. Cycle
I
SB
(TTL Inputs)
CMOS Standby Current /CS
>
V
CC
-0.2V, V
IN
>
I
SB1
(CMOS Inputs)
L
V
CC
-0.2V or V
IN
<
0.2V
V
OL
Output Low Voltage
I
OL
= 8.0mA
V
OH
Output High Voltage
I
OH
= -4.0mA
Note : Typical values are at Vcc = 3.3V, T
A
= 25°C
Min
-2
-2
-
-
-
-
-
-
-
2.4
Typ
-
-
-
-
-
-
-
-
-
Max
2
2
200
190
180
60
5
0.5
0.4
-
Unit
uA
uA
mA
mA
mA
mA
mA
mA
V
V
Rev.02 / Jan.99
2
HY63V8100A Series
AC CHARACTERISTICS
(Vcc = 3.3V ± 0.3V, T
A
= 0°C to 70°C, unless otherwise specified.)
8ns
#
Symbol
Parameter
Min Max
10ns
Min Max
10
-
-
-
3
0
0
0
3
10
7
7
0
7
10
0
0
5
0
3
-
10
10
5
-
-
5
5
-
-
-
-
-
-
-
-
5
-
-
-
12ns
Min Max
12
-
-
-
3
0
0
0
3
12
8
8
0
8
12
0
0
6
0
3
-
12
12
6
-
-
6
6
-
-
-
-
-
-
-
-
6
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ CYCLE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
tWC
tCW
tAW
tAS
tWP
tWP1
tWR
tWHZ
tDW
tDH
tOW
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Deselecting to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width(/OE High)
Write Pulse Width(/OE Low)
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
8
-
-
-
3
0
0
0
3
8
6
6
0
6
8
0
0
4
0
3
-
8
8
4
-
-
5
5
-
-
-
-
-
-
-
-
4
-
-
-
WRITE CYCLE
NOTE : Above parameters are also guaranteed at industrial temperature range.
Rev.02 / Jan.99
3
HY63V8100A Series
AC TEST CONDITIONS
(Vcc = 3.3V ± 0.3V, T
A
= 0°C to 70°C, unless otherwise specified.)
Parameter
Value
Input Pulse Level
0V to 3V
Input Rise and Fall Time
3ns
Input and Output Timing Reference Level
1.5V
Output Load
See below
AC TEST CONDITIONS
Output Load (A)
Z
o
=50
Ω
Dout
R
L
=50Ω
Output Load (B)
(for tCHZ, tCLZ, tOHZ, tOLZ, tWHZ & tOW)
+
3.3V
Dout
353Ω
5pF *
V
L
= 1.5V
Note : *Including jig and scope capacitance
CAPACITANCE
Temp = 25°C, f= 1.0MHz
Symbol
Parameter
CIN
Input Capacitance
C
I/O
Input/Output Capacitance
Condition
V
IN
= 0V
V
I/O
= 0V
Max.
7
8
Unit
pF
pF
Note : This parameter is sampled and not 100% tested
Rev.02 / Jan.99
4
HY63V8100A Series
TIMING DIAGRAM
READ CYCLE 1
tRC
ADDR
tAA
OE
tOE
tOLZ
CS
tACS
tCLZ
Data
Out
High-Z
Data Valid
tOHZ
tCHZ
tOH
Note (Read Cycle)
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels.
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.
3. /WE is high for read cycle.
READ CYCLE 2
tRC
ADDR
tAA
tOH
Data
Out
Previous Data
Data Valid
tOH
Note (Read Cycle)
1. /WE is high for read cycle.
2. Device is continuously selected /CS=V
IL
.
3. /OE=V
IL
.
Rev.02 / Jan.99
5
