March 2008
H Y B 18 T C 1G8 0 0 CF
H Y B 18 T C 1G1 6 0 CF
1-Gbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.00
Internet Data Sheet
HYB18TC1G[80/16]0CF
1-Gbit Double-Data-Rate-Two SDRAM
Revision History: Rev. 1.00, 2008-02
Adapted internet edition
Created revision 1.00
Previous Revision: Rev. 0.51, 2007-12
Corrected all figures in chapter 7 and chapter 8
Previous Revision: Rev. 0.50, 2007-08
First revision
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qag_techdoc_A4, 4.20, 2008-01-25
08162007-BC92-BZIO
2
Internet Data Sheet
HYB18TC1G[80/16]0CF
1-Gbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 1-Gbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 1-Gbit Double-Data-Rate-Two SDRAM offers the following key features:
• Posted CAS by programmable additive latency for better
• 1.8 V
±
0.1 V Power Supply
1.8 V
±
0.1 V (SSTL_18) compatible I/O
command and data bus efficiency
• DRAM organizations with 8,16 data in/outputs
• Off-Chip-Driver impedance adjustment (OCD) and
• Double Data Rate architecture:
On-Die-Termination (ODT) for better signal quality
– two data transfers per clock cycle
• Auto-Precharge operation for read and write bursts
– eight internal banks for concurrent operation
• Auto-Refresh, Self-Refresh and power saving Power-
• Programmable CAS Latency: 3, 4, 5 and 6
Down modes
• Programmable Burst Length: 4 and 8
• Average Refresh Period 7.8
μs
at a
T
CASE
lower
• Differential clock inputs (CK and CK)
than 85 °C, 3.9
μs
between 85 °C and 95 °C
• Bi-directional, differential data strobes (DQS and DQS) are
• Programmable self refresh rate via EMRS2 setting
transmitted / received with data. Edge aligned with read
• Programmable partial array refresh via EMRS2 settings
data and center-aligned with write data.
• DCC enabling via EMRS2 setting
• DLL aligns DQ and DQS transitions with clock
• Full and reduced Strength Data-Output Drivers
• 1KB page size for ×8, 2KB page size for ×16
• DQS can be disabled for single-ended data strobe
operation
• Packages: PG-TFBGA-60, PG-TFBGA-84
• Commands entered on each positive clock edge, data and
• RoHS Compliant Products
1)
data mask are referenced to both edges of DQS
• All Speed grades faster than DDR2–400 comply with
• Data masks (DM) for write data
DDR2–400 timing specifications when run at a clock rate
of 200 MHz.
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
For more information please visit
www.qimonda.com/green_products.
Rev. 1.00, 2008-03
08162007-BC92-BZIO
3
Internet Data Sheet
HYB18TC1G[80/16]0CF
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency CL3
CL4
CL5
CL6
CL7
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
DDR2
–19F
–1066E
6–6–6
–1.9
–1066F
7–7–7
–
266
333
400
533
13.125
13.125
45
58.125
–25F
–800D
5–5–5
200
266
400
–
–
12.5
12.5
45
57.5
–2.5
–800E
6–6–6
200
266
333
400
–
15
15
45
60
–3S
–667D
5–5–5
200
266
333
–
–
15
15
45
60
–3.7
–533C
4–4–4
200
266
266
–
–
15
15
45
60
–5
–400B
3–3–3
200
200
–
–
–
15
15
40
55
Unit
Note
t
CK
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
1)2)
13.125
15
15
17.5
18
18.75
20
ns
Precharge-All (8 banks)
command period
1) This
t
PREA
value is the minimum value at which this chip will be functional.
2) Precharge-All command for an 8 bank device will equal to
t
RP
+ 1 ×
t
CK
or
t
nRP
+ 1 × nCK, depending on the speed bin,
where
t
nRP
= RU{
t
RP
/
t
CK(avg)
} and
t
RP
is the value for a single bank precharge.
f
CK3
f
CK4
f
CK5
f
CK6
f
CK7
t
RCD
t
RP
t
RAS
t
RC
t
PREA
–
333
400
533
533
11.25
11.25
45
56.25
1.2
Description
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 17 bit address bus for ×8 organised components and a
16 bit address bus for ×16 components is used to convey row,
column and bank address information in a RAS-CAS
multiplexing style.
The DDR2 device operates with a 1.8 V
±
0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in TFBGA package.
The 1-Gbit DDR2 DRAM is a high-speed Double-Data-Rate-
Two CMOS Synchronous DRAM device containing
1,073,741,824 bits and internally configured as an octal bank
DRAM.
The 1-Gbit device is organized as 16 Mbit
×8
I/O
×8
banks or
8 Mbit
×16
I/O
×8
banks chip.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1
for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
Rev. 1.00, 2008-03
08162007-BC92-BZIO
4
Internet Data Sheet
HYB18TC1G[80/16]0CF
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
Org. Speed
CAS-RCD-RP
Latencies
2)3)4)
Clock (MHz) Package
Note
Standard Temperature Range (0 °C - +85 °C)
DDR2-1066F( 7-7-7 )
HYB18TC1G160CF-1.9
HYB18TC1G800CF-1.9
DDR2-1066E( 6-6-6 )
HYB18TC1G160CF-19F
HYB18TC1G800CF-19F
DDR2-800E( 6-6-6 )
HYB18TC1G800CF-2.5
HYB18TC1G160CF-2.5
DDR2-800D( 5-5-5 )
HYB18TC1G160CF-25F
HYB18TC1G800CF-25F
DDR2-667D( 5-5-5 )
HYB18TC1G160CF-3S
HYB18TC1G800CF-3S
DDR2-533C( 4-4-4 )
HYB18TC1G160CF-3.7
HYB18TC1G800CF-3.7
DDR2-400B( 3-3-3 )
HYB18TC1G160CF-5
HYB18TC1G800CF-5
1)
2)
3)
4)
5)
×16
×8
×16
×8
×8
×16
×16
×8
×16
×8
×16
×8
×16
×8
DDR2-1066F 7-7-7
DDR2-1066F 7-7-7
DDR2-1066E 6-6-6
DDR2-1066E 6-6-6
DDR2-800E
DDR2-800E
DDR2-800D
DDR2-800D
DDR2-667D
DDR2-667D
DDR2-533C
DDR2-533C
DDR2-400B
DDR2-400B
6-6-6
6-6-6
5-5-5
5-5-5
5-5-5
5-5-5
4-4-4
4-4-4
3-3-3
3-3-3
533
533
533
533
400
400
400
400
333
333
266
266
200
200
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
5)
For detailed information regarding product type of Qimonda please see chapter "Product Nomenclature" of this data sheet.
CAS: Column Address Strobe
RCD: Row Column Delay
RP: Row Precharge
RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit
www.qimonda.com/green_products.
Note: Please check with your Qimonda representative that leadtime and availability of your preferred device type and version
meet your project requirements.
Rev. 1.00, 2008-03
08162007-BC92-BZIO
5
