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HYB25D512400/800/160AT(L)

512-MBit Double Data Rata SDRAM

Preliminary Datasheet V0.91, 2002-11-14

Features

CAS Latency and Frequency

CAS Latency

2.5

Maximum Operating Frequency (MHz)

DDR200

DDR266A

DDR333

-8

-7

-6

100

133

125

143

166

• Double data rate architecture: two data transfers

per clock cycle

• Bidirectional data strobe (DQS) is transmitted

and received with data, to be used in capturing

data at the receiver

• DQS is edge-aligned with data for reads and is

center-aligned with data for writes

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge;

data and data mask referenced to both edges of

DQS

• Burst Lengths: 2, 4, or 8

• CAS Latency: (1.5), 2, 2.5, 3

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• 7.8

s Maximum Average Periodic Refresh

Interval

• 2.5V (SSTL_2 compatible) I/O

• V

DDQ

= 2.5V

0.2V

• V

= 2.5V

0.2V

• TSOP66 package

Description

The 512Mb DDR SDRAM is a high-speed CMOS,

dynamic random-access memory containing 536,870,912

bits. It is internally configured as a quad-bank DRAM.

The 512Mb DDR SDRAM uses a double-data-rate archi-

tecture to achieve high-speed operation. The double data

rate architecture is essentially a

prefetch architecture

with an interface designed to transfer two data words per

clock cycle at the I/O pins. A single read or write access

for the 512Mb DDR SDRAM effectively consists of a sin-

gle

2n-bit

wide, one clock cycle data transfer at the inter-

nal DRAM core and two corresponding n-bit wide, one-

half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver.

DQS is a strobe transmitted by the DDR SDRAM during

Reads and by the memory controller during Writes. DQS

is edge-aligned with data for Reads and center-aligned

with data for Writes.

The 512Mb DDR SDRAM operates from a differential

clock (CK and CK; the crossing of CK going HIGH and CK

going LOW is referred to as the positive edge of CK).

Commands (address and control signals) are registered at

every positive edge of CK. Input data is registered on both

edges of DQS, and output data is referenced to both

edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and con-

tinue for a programmed number of locations in a pro-

grammed sequence. Accesses begin with the registration

of an Active command, which is then followed by a Read

or Write command. The address bits registered coincident

with the Active command are used to select the bank and

row to be accessed. The address bits registered coinci-

V0.91, 2002-11-14

dent with the Read or Write command are used to select

the bank and the starting column location for the burst

access.

The DDR SDRAM provides for programmable Read or

Write burst lengths of 2, 4 or 8 locations. An Auto Pre-

charge function may be enabled to provide a self-timed

row precharge that is initiated at the end of the burst

access.

As with standard SDRAMs, the pipelined, multibank archi-

tecture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row

precharge and activation time.

An auto refresh mode is provided along with a power-sav-

ing power-down mode. All inputs are compatible with the

JEDEC Standard for SSTL_2. All outputs are SSTL_2,

Class II compatible.

Note:

The functionality described and the timing specifi-

cations included in this data sheet are for the DLL Enabled

mode of operation.

Page 1 of 77

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Ordering Information

Part Number (INF)

HYB25D512400AT(L)-8 *)

HYB25D512800AT(L)-8

HYB25D512160AT(L)-8

125

100

DDR200

CAS

Latency

Clock

(MHz)

CAS

Latency

Clock

(MHz)

Speed

Org.

x 16

Package

HYB25D512400AT(L)-7

HYB25D512800AT(L)-7

HYB25D512160AT(L)-7

2.5

143

133

DDR266A

x 16

66 pin TSOP-II

HYB25D512400AT(L)-6

HYB25D512800AT(L)-6

HYB25D512160AT(L)-6

*) Low Power Versions have a “L” in the partnumber, e. g. HYB25D512400ATL-8.

These components are specifically selected for low IDD6 Self Refresh currents.

166

133

DDR333

x 16

Page 2 of 77

V0.91, 2002-11-14

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Pin Configuration TSOP66

DDQ

DQ0

SSQ

DDQ

DQ1

SSQ

DDQ

CAS

RAS

BA0

BA1

A10/AP

DQ0

DDQ

DQ1

SSQ

DQ2

DDQ

DQ3

SSQ

DDQ

CAS

RAS

BA0

BA1

A10/AP

DQ0

DDQ

DQ1

DQ2

SSQ

DQ3

DQ4

DDQ

DQ5

DQ6

SSQ

DQ7

DDQ

LDQS

LDM

CAS

RAS

BA0

BA1

A10/AP

32Mb x 16

64Mb x 8

128Mb x 4

DQ15

SSQ

DQ14

DQ13

DDQ

DQ12

DQ11

SSQ

DQ10

DQ9

DDQ

DQ8

SSQ

UDQS

REF

UDM

CKE

A12

A11

DQ7

SSQ

DQ6

DDQ

DQ5

SSQ

DQ4

DDQ

SSQ

DQS

REF

CKE

A12

A11

SSQ

DQ3

DDQ

SSQ

DQ2

DDQ

SSQ

DQS

REF

CKE

A12

A11

Page 3 of 77

V0.91, 2002-11-14

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Input/Output Functional Description

Symbol

CK, CK

Type

Input

Function

Clock:

CK and CK are differential clock inputs. All address and control input signals are sam-

pled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data

is referenced to the crossings of CK and CK (both directions of crossing).

Clock Enable:

CKE HIGH activates, and CKE Low deactivates, internal clock signals and

device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down

and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank).

CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asyn-

chronous for self refresh exit. CKE must be maintained high throughout read and write

accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input

buffers, excluding CKE, are disabled during self refresh.

Chip Select:

All commands are masked when CS is registered HIGH. CS provides for exter-

nal bank selection on systems with multiple banks. CS is considered part of the command

code. The standard pinout includes one CS pin.

Command Inputs:

RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask:

DM is an input mask signal for write data. Input data is masked when DM

is sampled HIGH coincident with that input data during a Write access. DM is sampled on

both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and

DQS loading.

Bank Address Inputs:

BA0 and BA1 define to which bank an Active, Read, Write or Pre-

charge command is being applied. BA0 and BA1 also determines if the mode register or

extended mode register is to be accessed during a MRS or EMRS cycle.

Address Inputs:

Provide the row address for Active commands, and the column address

and Auto Precharge bit for Read/Write commands, to select one location out of the memory

array in the respective bank. A10 is sampled during a Precharge command to determine

whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one

bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide

the op-code during a Mode Register Set command.

Data Input/Output:

Data bus.

Data Strobe:

Output with read data, input with write data. Edge-aligned with read data, cen-

tered in write data. Used to capture write data.

No Connect:

No internal electrical connection is present.

Supply

DQ Power Supply:

2.5V

0.2V.

DQ Ground

Power Supply:

2.5V

0.2V.

Ground

SSTL_2 reference voltage:

DDQ

/ 2)

CKE

Input

RAS, CAS, WE

Input

BA0, BA1

Input

A0 - A12

Input

DQS

DDQ

SSQ

REF

Input/Output

Page 4 of 77

V0.91, 2002-11-14

HYB25D512400/800/160AT(L)/AC(L)

512-Mbit Double Data Rate SDRAM

Block Diagram (128Mbit x 4)

Control Logic

CKE

CAS

RAS

Command

Decode

Bank1

Row-Address MUX

Bank0

Row-Address Latch

& Decoder

Bank2

Bank3

CK, CK

DLL

Mode

Registers

8192

Read Latch

Refresh Counter 13

MUX

DQS

Generator

Sense Amplifiers

Bank Control Logic

16384

Drivers

Bank0

Memory

Array

(8192 x 2048 x 8)

Data

Address Register

COL0

I/O Gating

DM Mask Logic

2048

(x8)

Column

Decoder

Write

FIFO

Drivers

clk clk

out in Data

CK,

COL0

Column-Address

Counter/Latch

COL0

Note:

This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note:

DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

Receivers

A0-A12,

BA0, BA1

Input

Mask 1

DQS

DQ0-DQ3,

DQS

Page 5 of 77

V0.91, 2002-11-14