16M x 4-Bit Dynamic RAM
(4k & 8k Refresh)
HYB 3164400AJ/AT(L) -40/-50/-60
HYB 3165400AJ/AT(L) -40/-50/-60
Advanced Information
•
•
•
•
16 777 216 words by 4-bit organization
0 to 70 °C operating temperature
Fast Page Mode operation
Performance:
-40
t
RAC
t
CAC
t
AA
t
RC
t
PC
RAS access time
CAS access time
Access time from address
Read/write cycle time
Fast page mode cycle time
40
10
20
75
30
-50
50
13
25
90
35
-60
60
15
30
110
40
ns
ns
ns
ns
ns
•
•
Single + 3.3 V (± 0.3V) power supply
Low power dissipation:
max. 396 mW active ( HYB 3164400AJ/AT(L) -40)
max. 324 mW active ( HYB 3164400AJ/AT(L) -50)
max. 270 mW active ( HYB 3164400AJ/AT(L) -60)
max. 558 mW active ( HYB 3165400AJ/AT(L) -40)
max. 468 mW active ( HYB 3165400AJ/AT(L) -50)
max. 378 mW active ( HYB 3165400AJ/AT(L) -60)
7.2 mW standby (LVTTL)
3.24 mW standby (LVCMOS)
720
µW
standby for L-versions
Read, write, read-modify-write, CAS-before-RAS refresh (CBR),
RAS-only refresh, hidden refresh and self refresh (L-version only)
•
8192 refresh cycles/128 ms , 13 R/ 11C addresses (HYB 3164400AJ/AT)
4096 refresh cycles/ 64 ms , 12 R/ 12C addresses (HYB 3165400AJ/AT)
•
256 msec refresh period for L-versions
•
•
Plastic Package
P-SOJ-32-1
400 mil
P-TSOPII-32-1 400 mil
HYB 3164(5)400AJ
HYB 3164(5)400AT
Semiconductor Group
1
6.97
HYB3164(5)400AJ/AT(L)-40/-50/-60
16M x 4-DRAM
This device is a 64 MBit dynamic RAM organized 16 777 216 by 4 bits. The device is fabricated on
an advanced second generation 64Mbit 0,35
µm-CMOS
silicon gate process technology. The circuit
and process design allow this device to achieve high performance and low power dissipation. This
DRAM operates with a single 3.3 +/-0.3V power supply and interfaces with either LVTTL or
LVCMOS levels. Multiplexed address inputs permit the HYB 3164(5)400AJ/AT to be packaged in a
400mil wide SOJ-32 or TSOP-32 plastic package. These packages provide high system bit
densities and are compatible with commonly used automatic testing and insertion equipment. The
HYB3164(5)400ATL parts (L-versions) have a very low power „sleep mode“ supported by Self
Refresh
Ordering Information
Type
HYB 3164400AJ-40
HYB 3164400AJ-50
HYB 3164400AJ-60
HYB 3164400AT-40
HYB 3164400AT-50
HYB 3164400AT-60
HYB 3165400AJ-40
HYB 3165400AJ-50
HYB 3165400AJ-60
HYB 3165400AT-40
HYB 3165400AT-50
HYB 3165400AT-60
HYB 3164(5)400ATL
Ordering
Code
Package
P-SOJ-32-1
P-SOJ-32-1
P-SOJ-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-SOJ-32-1
P-SOJ-32-1
P-SOJ-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
P-TSOPII-32-1
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
400 mil
Descriptions
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 40 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
Low Power DRAMs
Pin Names
A0-A12
A0-A11
RAS
OE
I/O1-I/O4
CAS
WE
Vcc
Vss
Address Inputs for 8k-refresh versions HYB 3164400AJ/AT(L)
Address Inputs for 4k-refresh versions HYB 3165400AJ/AT(L)
Row Address Strobe
Output Enable
Data Input/Output
Column Address Strobe
Read/Write Input
Power Supply ( + 3.3V)
Ground
Semiconductor Group
2
HYB3164(5)400AJ/AT(L)-40/-50/-60
16M x 4-DRAM
P-SOJ-32-1 (400 mil)
P-TSOPII-32-1 (400 mil)
VCC
I/O1
I/O2
N.C.
N.C.
N.C.
N.C.
WRITE
RAS
.
A0
A1
A2
A3
A4
A5
VCC
O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
I/O4
I/O3
N.C.
N.C.
N.C.
CAS
OE
A12 / N.C. *
A11
A10
A9
A8
A7
A6
VSS
* Pin 24 is A12 for HYB 3164400AJ/AT(L) and N.C. for HYB 3165400AJ/AT(L)
Pin Configuration
Semiconductor Group
3
HYB3164(5)400AJ/AT(L)-40/-50/-60
16M x 4-DRAM
TRUTH TABLE
FUNCTION
Standby
Read
Early-Write
Delayed-Write
Read-Modify-Write
Fast Page Mode Read
1st Cycle
2nd Cycle
Fast Page Mode Early
Write
1st Cycle
2nd Cycle
Fast Page Mode RMW
1st Cycle
2st Cycle
RAS only refresh
CAS-before-RAS refresh
Test Mode Entry
Hidden Refresh
READ
WRITE
RAS
H
L
L
L
L
L
L
L
L
L
L
L
H-L
H-L
L-H-L
L-H-L
CAS
H-X
L
L
L
L
H-L
H-L
H-L
H-L
H-L
H-L
H
L
L
L
L
WE
X
H
L
H-L
H-L
H
H
L
L
H-L
H-L
X
H
L
H
L
OE
X
L
X
H
L-H
L
L
X
X
L-H
L-H
X
X
X
L
X
ROW
ADDR
X
ROW
ROW
ROW
ROW
ROW
n/a
ROW
n/a
ROW
n/a
ROW
X
X
ROW
ROW
COL
ADDR
X
COL
COL
COL
COL
COL
COL
COL
COL
COL
COL
n/a
n/a
n/a
COL
COL
I/O1-
I/O4
High Impedance
Data Out
Data In
Data In
Data Out, Data In
Data Out
Data Out
Data In
Data In
Data Out, Data In
Data Out, Data In
High Impedance
High Impedance
High Impedance
Data Out
Data In
Semiconductor Group
4
HYB3164(5)400AJ/AT(L)-40/-50/-60
16M x 4-DRAM
I/O1
I
/O2
I/O4
WE
CAS
.
&
Data in
Buffer
No. 2 Clock
Generator
4
Data out
Buffer
4
OE
12
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
12
Column
Address
Buffer(12)
12
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
4
Refresh
Counter (12)
12
Row
4096
x4
Address
Buffers(12)
12
Decoder
4096
4096 x 4096 x 4
Row
Memory Array
RAS
No. 1 Clock
Generator
Block Diagram for HYB 3165400AJ/AT(L)
Semiconductor Group
5
