HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
128-MBit Synchronous DRAM
Preliminary Target Specification 10.01
High Performance:
-6
-7
143
7
5.4
7.5
5.4
-7.5
133
7.5
5.4
10
6
-8
125
8
6
10
6
Units
MHz
ns
ns
ns
ns
• Multiple Burst Read with Single Write
Operation
• Automatic and Controlled Precharge
Command
• Data Mask for Read/Write Control (x4, x8)
• Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Power Down and Clock Suspend Mode
• 4096 Refresh Cycles / 64 ms
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• 0 to 70
°
C operating temperature
• Four Banks controlled by BA0 & BA1
• Programmable CAS Latency: 2, 3
• Programmable Wrap Sequence: Sequential
or Interleave
• Programmable Burst Length:
1, 2, 4, 8 and full page
• Random Column Address every CLK
(1-N Rule)
• Single 3.3 V
±
0.3 V Power Supply
• LVTTL Interface
• Plastic Packages:
P-TSOPII-54 400mil x 875 mil width
(x4, x8, x16)
• -6
-7
-7.5
-8
for
for
for
for
PC 166 3-3-3 applications
PC 133 2-2-2 applications
PC 133 3-3-3 applications
PC100 2-2-2 applications
f
CK
t
CK3
t
AC3
t
CK2
t
AC2
166
6
5
7.5
5.4
The HYB 39S128400/800/160DT(L) are four bank Synchronous DRAM’s organized as 4
banks
×
8MBit x4, 4 banks
×
4MBit x8 and 4 banks
×
2Mbit x16 respectively. These synchronous
devices achieve high speed data transfer rates by employing a chip architecture that prefetches
multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using
the Infineon advanced 0.17 micron process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher a rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3 V
±
0.3 V power supply and are available in TSOPII packages.
INFINEON Technologies
1
10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Ordering Information
Type
HYB 39S128400DT-6
HYB 39S128400DT-7
HYB 39S128400DT-7.5
HYB 39S128400DT-8
HYB 39S128800DT-6
HYB 39S128800DT-7
HYB 39S128800DT-7.5
HYB 39S128800DT-8
HYB 39S128160DT-6
HYB 39S128160DT-7
HYB 39S128160DT-7.5
HYB 39S128160DT-8
HYB 39S128160DTL-8
HYB 39S128160DTL-7.5
HYB 39S128160DTL-7
Function Code Package
Description
PC166-333-520 P-TSOP-54 (400mil)
166MHz 4B
×
8M x4 SDRAM
PC133-222-520 P-TSOP-54 (400mil)
143MHz 4B
×
8M x4 SDRAM
PC133-333-520 P-TSOP-54 (400mil)
133 MHz 4B
×
8M x4 SDRAM
PC100-222-620 P-TSOP-54 (400mil)
100 MHz 4B
×
8M x4 SDRAM
PC166-333-520 P-TSOP-54 (400mil)
166 MHz 4B
×
4M x8 SDRAM
PC133-222-520 P-TSOP-54 (400mil)
143 MHz 4B
×
4M x8 SDRAM
PC133-333-520 P-TSOP-54 (400mil)
133 MHz 4B
×
4M x8 SDRAM
PC100-222-620 P-TSOP-54 (400mil)
100 MHz 4B
×
4M x8 SDRAM
PC166-333-520 P-TSOP-54 (400mil)
166 MHz 4B
×
2M x16 SDRAM
PC133-222-520 P-TSOP-54 (400mil)
143 MHz 4B
×
2M x16 SDRAM
PC133-333-520 P-TSOP-54 (400mil)
133 MHz 4B
×
2M x16 SDRAM
PC100-222-620 P-TSOP-54 (400mil)
100 MHz 4B
×
2M x16 SDRAM
PC100-222-620 P-TSOP-54 (400mil)
100 MHz 4B
×
2M x16 SDRAM
Low Power (“L”) version
PC133-333-520 P-TSOP-54 (400mil)
133 MHz 4B
×
2M x16 SDRAM
Low Power (“L”) version
PC133-222-520 P-TSOP-54 (400mil)
133 MHz 4B
×
2M x16 SDRAM
Low Power (“L”) version
Pin Definitions and Functions
CLK
CKE
CS
RAS
CAS
WE
A0 - A11
BA0, BA1
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
DQ
DQM, LDQM,
UDQM
Data Input/Output
Data Mask
Power (+ 3.3 V)
Ground
Power for DQ’s (+ 3.3 V)
Ground for DQ’s
Not connected
V
DD
V
SS
V
DDQ
V
SSQ
N.C.
INFINEON Technologies
2
10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
8 M x 16
16 M x 8
32 M x 4
V
DD
DQ0
V
DD
DQ0
V
DD
N.C.
V
DDQ
DQ1
DQ2
V
DDQ
N.C.
DQ1
V
DDQ
N.C.
DQ0
V
SSQ
DQ3
DQ4
V
SSQ
N.C.
DQ2
V
SSQ
N.C.
N.C.
V
DDQ
DQ5
DQ6
V
DDQ
N.C.
DQ3
V
DDQ
N.C.
DQ1
V
SSQ
DQ7
V
SSQ
N.C.
V
SSQ
N.C.
V
DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
N.C.
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
N.C.
WE
CAS
RAS
CS
BA0
BA1
A10
A0
A1
A2
A3
V
DD
V
DD
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
N.C.
V
SS
DQ7
V
SS
DQ15
V
SSQ
N.C.
DQ3
V
SSQ
N.C.
DQ6
V
SSQ
DQ14
DQ13
V
DDQ
N.C.
N.C.
V
DDQ
N.C.
DQ5
V
DDQ
DQ12
DQ11
V
SSQ
N.C.
DQ2
V
SSQ
N.C.
DQ4
V
SSQ
DQ10
DQ9
V
DDQ
N.C.
V
DDQ
N.C.
V
DDQ
DQ8
V
SS
N.C.
DQM
CLK
CKE
N.C.
A11
A9
A8
A7
A6
A5
A4
V
SS
N.C.
DQM
CLK
CKE
N.C.
A11
A9
A8
A7
A6
A5
A4
V
SS
N.C.
UDQM
CLK
CKE
N.C.
A11
A9
A8
A7
A6
A5
A4
V
SS
V
SS
V
SS
TSOPII-54 (10.16 mm x 22.22 mm, 0.8 mm pitch)
SPP04121
Pin Configuration for x4, x8 & x16 Organized 128M-DRAMs
INFINEON Technologies
3
10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Functional Block Diagrams
Column Addresses
A0 - A9, A11, AP,
BA0, BA1
Row Addresses
A0 - A11,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Bank 0
4096
x 2048
x 4 Bit
Bank 1
4096
x 2048
x 4 Bit
Bank 2
4096
x 2048
x 4 Bit
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Bank 3
4096
x 2048
x 4 Bit
Input Buffer
Output Buffer
Control Logic &
Timing Generator
DQ0 - DQ3
Block Diagram: 32M x4 SDRAM (12 / 11 / 2 addressing)
INFINEON Technologies
4
CLK
CKE
CS
RAS
CAS
WE
DQM
SPB04122
10.01
HYB 39S128400/800/160DT(L)
128-MBit Synchronous DRAM
Column Addresses
A0 - A9, AP,
BA0, BA1
Row Addresses
A0 - A11,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row
Decoder
Row
Decoder
Row
Decoder
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Bank 0
4096
x 1024
x 8 Bit
Bank 1
4096
x 1024
x 8 Bit
Bank 2
4096
x 1024
x 8 Bit
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Memory
Array
Memory
Array
Memory
Array
Bank 3
4096
x 1024
x 8 Bit
Input Buffer
Output Buffer
Control Logic &
Timing Generator
DQ0 - DQ7
Block Diagram: 16M x8 SDRAM (12 / 10 / 2 addressing)
INFINEON Technologies
5
CLK
CKE
CS
RAS
CAS
WE
DQM
SPB04123
10.01
