HYB39S512400/800/160AT(L)
512MBit Synchronous DRAM
512 MBit Synchronous DRAM
Preliminary Datasheet April ’01
•
High Performance:
-6
fCK
tCK3
tAC3
tCK2
tAC2
166
6
5
7.5
5.4
-7
143
7
5.4
7.5
5.4
-7.5
133
7.5
5.4
10
6
-8
125
8
6
10
6
Units
MHz
ns
ns
ns
ns
•
•
•
•
•
•
•
•
•
•
•
•
Multiple Burst Read with Single Write
Operation
Automatic
Command
and
Controlled
Precharge
Data Mask for Read / Write control (x4, x8)
Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Power Down and Clock Suspend Mode
8192 refresh cycles / 64 ms (7,8
µs)
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface versions
Plastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
-6 parts for PC166 3-3-3 operation
-7 parts for PC133 2-2-2 operation
-7.5 parts for PC133 3-3-3 operation
-8 parts for PC100 2-2-2 operation
•
•
•
•
•
•
Fully Synchronous to Positive Clock Edge
0 to 70
°C
operating temperature
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2 & 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
1, 2, 4, 8 and full page
The HYB39S512400/800/160AT(L) are four bank Synchronous DRAM’s organized as 4 banks x
32MBit x4, 4 banks x 16MBit x8 and 4 banks x 8Mbit x16 respectively. These synchronous devices
achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that
prefetches multiple bits and then synchronizes the output data to a system clock. The chip is
fabricated with INFINEON’s advanced 0.14
µm
512MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible
depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a
single 3.3V +/- 0.3V power supply. All 512Mbit components are housed in TSOPII-54 packages.
INFINEON Technologies
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4.01
HYB39S512400/800/160AT(L)
512MBit Synchronous DRAM
Ordering Information
Type
Speed Grade
Package
Description
HYB 39S512400AT-6
HYB 39S512400AT-7
HYB 39S512400AT-7.5
HYB 39S512400AT-8
HYB 39S512800AT-6
HYB 39S512800AT-7
HYB 39S512800AT-7.5
HYB 39S512800AT-8
HYB 39S512160AT-6
HYB 39S512160AT-7
HYB 39S512160AT-7.5
HYB 39S512160AT-8
HYB39S512xx0ATL
PC166-333-520
PC133-222-520
PC133-333-520
PC100-222-620
PC166-333-520
PC133-222-520
PC133-333-520
PC100-222-620
PC166-333-520
PC133-222-520
PC133-333-520
PC100-222-620
PC100-xxx-620
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
P-TSOP-54-2 (400mil)
166MHz 4B x 32M x 4 SDRAM
143MHz 4B x 32M x 4 SDRAM
133MHz 4B x 32M x 4 SDRAM
125MHz 4B x 32M x 4 SDRAM
166MHz 4B x 16M x 8 SDRAM
143MHz 4B x 16M x 8 SDRAM
133MHz 4B x 16M x 8 SDRAM
125MHz 4B x 16M x 8 SDRAM
166MHz 4B x 8M x 16 SDRAM
143MHz 4B x 8M x 16 SDRAM
133MHz 4B x 8M x 16 SDRAM
125MHz 4B x 8M x 16 SDRAM
Low Power Versions (on request)
Pin Description
CLK
CKE
CS
RAS
CAS
WE
A0-A12
BA0, BA1
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Address Inputs
Bank Select
DQx
DQM, LDQM, UDQM
V
DD
V
SS
V
DDQ
V
SSQ
NC
Data Input /Output
Data Mask
Power (+3.3V)
Ground
Power for DQ’s (+ 3.3V)
Ground for DQ’s
not connected
INFINEON Technologies
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4.01
HYB39S512400/800/160AT(L)
512MBit Synchronous DRAM
Pinouts:
32M x 16
64M x 8
128M x 4
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD VDD
DQ0 NC
VDDQ VDDQ
NC
NC
DQ1 DQ0
VSSQ VSSQ
NC
NC
DQ2 NC
VDDQ VDDQ
NC
NC
DQ3 DQ1
VSSQ VSSQ
NC
NC
VDD VDD
NC
NC
WE
WE
CAS CAS
RAS RAS
CS
CS
BA0
BA0
BA1
BA1
A10/APA10/AP
A0
A0
A1
A1
A2
A2
A3
A3
VDD VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
VSS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
VSS
TSOPII-54 (400 mil x 875 mil, 0.8 mm pitch)
Pinout for x4, x8 & x16 organised 512M-DRAMs
INFINEON Technologies
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4.01
HYB39S512400/800/160AT(L)
512MBit Synchronous DRAM
Column Addresses
A0 - A9, AP,A11,A12
,
BA0, BA1
Row Addresses
A0 - A12,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Row
Decoder
Memory
Array
Bank 0
8192
x 4096
x 4 Bit
Bank 1
8192
x 4096
x 4 Bit
Bank 2
8192
x 4096
x 4 Bit
Bank 3
8192
x 4096
x 4 Bit
Input Buffer
Output Buffer
Control Logic &
Timing Generator
DQ0 - DQ3
CLK
CKE
CS
RAS
CAS
WE
DQM
Block Diagram for 128M x 4 SDRAM ( 13 / 12 / 2 addressing)
INFINEON Technologies
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4.01
HYB39S512400/800/160AT(L)
512MBit Synchronous DRAM
Column Addresses
A0 - A9, AP,A11
BA0, BA1
Row Addresses
A0 - A12,
BA0, BA1
Column Address
Counter
Column Address
Buffer
Row Address
Buffer
Refresh Counter
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Row
Decoder
Column Decoder
Sense amplifier & I(O) Bus
Memory
Array
Row
Decoder
Memory
Array
Bank 0
8192
x 2048
x 8 Bit
Bank 1
8192
x 2048
x 8 Bit
Bank 2
8192
x 2048
x 8 Bit
Bank 3
8192
x 2048
x 8 Bit
Input Buffer
Output Buffer
Control Logic &
Timing Generator
DQ0 - DQ7
CLK
CKE
CS
RAS
CAS
WE
DQM
Block Diagram for 64M x 8 SDRAM ( 13 / 11 / 2 addressing)
INFINEON Technologies
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4.01
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