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May 2008

HYB25DC512800D[E/F]

HYB25DC512160D[E/F]

H Y I2 5 DC 5128 0 0 D [ E / F ]

HYI25DC512160D[E/F](L)

5 1 2 - M b i t D o u b l e - D a t a - R a t e SD R A M

DDR SDRAM

EU RoHS Compliant Products

Internet Data Sheet

Rev. 1.10

Internet Data Sheet

HY[B/I]25DC512[80/16]0D[E/F](L)

512-Mbit Double-Data-Rate SDRAM

Revision History: Rev. 1.10, 2008-05

Adapted internet edition

Added product HYI25DC512160DEL-5

Corrected IOH to -16.2, IOL to 16.2 in chapter 5.1

Added new IDD values

Previous Revision: Rev. 0.60, 2007-11

Added new IDD values

Previous Revision: Rev. 1.00, 2008-03

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc@qimonda.com

qag_techdoc_A4, 4.20, 2008-01-25

06212007-08MW-K87L

Internet Data Sheet

HY[B/I]25DC512[80/16]0D[E/F](L)

512-Mbit Double-Data-Rate SDRAM

Overview

This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main

characteristics.

1.1

•

Features

Double data rate architecture: two data transfers per clock cycle

Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver

DQS is edge-aligned with data for reads and is center-aligned with data for writes

Differential clock inputs (CK and CK)

Four internal banks for concurrent operation

Data mask (DM) for write data

DLL aligns DQ and DQS transitions with CK transitions

Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

Programmable CAS latency: 2, 2.5, 3 and 4

Programmable burst lengths: 2, 4, or 8

Programmable drive strength: normal, weak

Auto Precharge option for each burst access

Auto Refresh and Self Refresh Modes

RAS-lockout supported

RAP

RCD

7.8

μs

Maximum Average Periodic Refresh Interval

2.5 V (SSTL_2 compatible) I/O

= 2.5 V

0.2 V,

= 2.6 V

0.1 V (DDR500)

DDQ

= 2.5 V

0.2 V,

DDQ

= 2.6 V

0.1 V (DDR500)

Packages: PG-TSOPII-66, PG-TFBGA-60

RoHS Compliant Products

TABLE 1

Performance

Part Number Speed Code

Speed Grade

Max. Clock Frequency

@CL4

@CL3

@CL2.5

@CL2

–4

DDR500B

–5A

DDR400A

200

133

–5

DDR400B

200

166

133

–6

DDR333B

166

133

Unit

—

MHz

CK4

CK3

CK2.5

CK2

250

200

133

1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.

For more information please visit

www.qimonda.com/green_products.

Rev. 1.10, 2008-05

06212007-08MW-K87L

Internet Data Sheet

HY[B/I]25DC512[80/16]0D[E/F](L)

512-Mbit Double-Data-Rate SDRAM

1.2

Description

Read and write accesses to the DDR SDRAM are burst

oriented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an Active

command, which is then followed by a Read or Write

command. The address bits registered coincident with the

Active command are used to select the bank and row to be

accessed. The address bits registered coincident with the

Read or Write command are used to select the bank and the

starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write

burst lengths of 2, 4 or 8 locations. An Auto Precharge

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst access. As

with standard SDRAMs, the pipelined, multibank architecture

of DDR SDRAMs allows for concurrent operation, thereby

providing high effective bandwidth by hiding row precharge

and activation time.

An auto refresh mode is provided along with a power-saving

power-down mode. All inputs are compatible with the Industry

Standard for SSTL_2. All outputs are SSTL_2, Class II

compatible.

Note: The functionality described and the timing

specifications included in this data sheet are for the

DLL Enabled mode of operation.

The 512-Mbit Double-Data-Rate SDRAM is a high-speed

CMOS, dynamic random-access memory containing 536,

870, 912 bits. It is internally configured as a quad-bank

DRAM.

The 512-Mbit Double-Data-Rate SDRAM uses a double-

data-rate architecture to achieve high-speed operation. The

double data rate architecture is essentially a 2n prefetch

architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write

access for the 512-Mbit Double-Data-Rate SDRAM

effectively consists of a single 2n-bit wide, one clock cycle

data transfer at the internal DRAM core and two

corresponding n-bit wide, one-half-clock-cycle data transfers

at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver. DQS

is a strobe transmitted by the DDR SDRAM during Reads and

by the memory controller during Writes. DQS is edge-aligned

with data for Reads and center-aligned with data for Writes.

The 512-Mbit Double-Data-Rate SDRAM operates from a

differential clock (CK and CK; the crossing of CK going HIGH

and CK going LOW is referred to as the positive edge of CK).

Commands (address and control signals) are registered at

every positive edge of CK. Input data is registered on both

edges of DQS, and output data is referenced to both edges of

DQS, as well as to both edges of CK.

TABLE 2

Ordering Information for RoHS Compliant Products

Product Type

Org. Speed

CAS-RCD-RP

Latencies

2)3)4)

Clock (MHz) Package

Note

Standard Temperature Range (0 °C - 70 °C)

DDR500B( 3-3-3 )

HYB25DC512160DE-4

HYB25DC512160DF-4

HYB25DC512800DE-4

HYB25DC512800DF-4

DDR400B( 3-3-3 )

HYB25DC512160DE-5

HYB25DC512160DF-5

HYB25DC512800DE-5

HYB25DC512800DF-5

DDR400A( 2.5-3-3 )

HYB25DC512160DE-5A

×16

DDR400A

2.5-3-3

200

PG-TSOPII-66

×16

×8

DDR400B

3-3-3

200

PG-TSOPII-66

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

×16

×8

DDR500B

3-3-3

250

PG-TSOPII-66

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

Rev. 1.10, 2008-05

06212007-08MW-K87L

Internet Data Sheet

HY[B/I]25DC512[80/16]0D[E/F](L)

512-Mbit Double-Data-Rate SDRAM

Product Type

HYB25DC512160DF-5A

HYB25DC512800DE-5A

HYB25DC512800DF-5A

DDR333B( 2.5-3-3 )

HYB25DC512160DE-6

HYB25DC512160DF-6

HYB25DC512800DE-6

HYB25DC512800DF-6

DDR500B( 3-3-3 )

HYI25DC512160DE-4

HYI25DC512160DF-4

HYI25DC512800DE-4

HYI25DC512800DF-4

DDR400B( 3-3-3 )

HYI25DC512160DEL-5

HYI25DC512160DE-5

HYI25DC512160DF-5

HYI25DC512800DE-5

HYI25DC512800DF-5

DDR400A( 2.5-3-3 )

HYI25DC512800DF-5A

HYI25DC512160DE-5A

HYI25DC512160DF-5A

HYI25DC512800DE-5A

DDR333B( 2.5-3-3 )

HYI25DC512160DE-6

HYI25DC512160DF-6

HYI25DC512800DE-6

HYI25DC512800DF-6

Org. Speed

×16

×8

×16

×8

DDR400A

DDR333B

CAS-RCD-RP

Latencies

2)3)4)

2.5-3-3

Clock (MHz) Package

200

166

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

Note

Industrial Temperature Range (--40 °C - 85 °C)

×16

×8

×16

×8

×16

×8

×16

×8

DDR500B

DDR400B

DDR400A

DDR333B

3-3-3

2.5-3-3

250

200

166

PG-TSOPII-66

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

PG-TSOPII-66

PG-TFBGA-60

For detailed information regarding product type of Qimonda please see chapter "Product Nomenclature" of this data sheet.

CAS: Column Address Strobe

RCD: Row Column Delay

RP: Row Precharge

RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined

in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,

lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. For more information please visit

www.qimonda.com/green_products.

Note: Please check with your Qimonda representative that leadtime and availability of your preferred device type and version

meet your project requirements.

Rev. 1.10, 2008-05

06212007-08MW-K87L