based on 16Mx16 SDRAM with LVTTL, 4 banks & 8K Refresh
HYM72V16M656H(L)T6 Series
DESCRIPTION
The HYM72V16M656H(L)T6 -Series are high speed 3.3-Volt Synchronous DRAM Modules composed of four 16Mx16 bit
Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit EEPROM on a 144-pin Zig Zag Dual pin glass-epoxy
printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are mounted on the module.
The HYM72V16M656H(L)T6 -Series are gold plated socket type Dual In-line Memory Modules suitable for easy inter-
change and addition of 128M bytes memory. All inputs and outputs are synchronized with the rising edge of the clock
input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
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PC100 support
144pin SDRAM SO DIMM
Serial Presence Detect with EEPROM
1.0” (25.4mm) Height PCB with double sided compo-
nents
Single 3.3±0.3V power supply
- 1, 2, 4 or 8 or Full page for Sequential Burst
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•
All device pins are compatible with LVTTL interface
- 1, 2, 4 or 8 for Interleave Burst
Data mask function by DQM
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Programmable CAS Latency ; 2, 3 Clocks
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SDRAM internal banks : four banks
Module bank : one physical bank
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
ORDERING INFORMATION
Part No.
HYM72V16M656HT6-P
HYM72V16M656HT6-S
HYM72V16M656HLT6-P
HYM72V16M656HLT6-S
Clock
Frequency
100MHz
100MHz
100MHz
100MHz
Internal
Bank
Ref.
Power
Normal
SDRAM
Package
Plating
4 Banks
8K
Low Power
TSOP-II
Gold
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1/Nov. 01
PC100 SDRAM SO DIMM
HYM72V16M656H(L)T6 Series
PIN DESCRIPTION
PIN
CK0, CK1
CKE0
/S0
BA0, BA1
A0 ~ A12
/RAS, /CAS, /WE
DQM0~DQM7
DQ0 ~ DQ63
VCC
V
SS
SCL
SDA
SA0~2
WP
NC
PIN NAME
Clock Inputs
Clock Enable
Chip Select
SDRAM Bank Address
Address
Row Address Strobe, Column
Address Strobe, Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3V)
Ground
SPD Clock Input
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
