3.3V 4M
×
64-Bit EDO-DRAM Module
3.3V 4M x 72-Bit EDO-DRAM Module
168pin unbuffered DIMM Module
with serial presence detect
Target Information
•
HYM64V4005GU-50/-60/-70
HYM64V4045GU-50/-60/-70
HYM72V4005GU-50/-60/-70
HYM72V4045GU-50/-60/-70
168 Pin JEDEC Standard, Unbuffered 8 Byte
Dual In-Line Memory Module
1 bank 4M x 64, 4M x 72 in 2k and 4k refresh organisations
Optimized for byte-write non-parity or ECC applications
Extended Data Out (EDO)
Performance:
-50
tRAC
tCAC
tAA
tRC
tHPC
RAS Access Time
CAS Access Time
Access Time from Address
Cycle Time
EDO Mode Cycle Time
50 ns
13 ns
25 ns
84 ns
20 ns
-60
60 ns
15 ns
30 ns
104 ns
25 ns
-70
70 ns
20 ns
35 ns
124 ns
30 ns
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single +3.3 V
±
0.3 V Power Supply
CAS-before-RAS refresh, RAS-only-refresh
Decoupling capacitors mounted on substrate
All inputs, outputs and clocks are fully LV-TTL compatible
Serial presence detects (optional)
Utilizes 4M x 4 -DRAMs in TSOPII packages
2048 refresh cycles / 32 ms with 11 / 11 addressing ( Row / Column) for HYM64/72V4005GU
4096 refresh cycles / 64 ms with 12 / 10 addressing ( Row / Column) for HYM64/72V4045GU
Gold contact pads
Card Size: 133,35mm x 25,40 mm x 4,00 mm
This DRAM product module family is intended to be fully pin and architecture compatible
with the 168pin unbuffered SDRAM DIMM module family
Semiconductor Group
1
3.96
HYM 64(72)V4005/45GU-50/-60/-70
4M x 64/72 DRAM Module
The HYM64(72)V4005/45GS-50/-60/-70 are industry standard 168-pin 8-byte Dual In-Line Memory
Modules (DIMMs) which are organized as 4M x 64 and 4M x 72 high speed memory arrays
designed with EDO DRAMs for non-parity and ECC applications. 2k refresh with 11 / 11 addressing
and 4k refresh modules with 12 / 10 addressing are available. The DIMMs use sixteen 4M x 4 EDO
DRAMs for the 4M x 64 organisation and eighteen 4M x 4 DRAMs for the 4M x 72 organisation, both
in TSOPII packages. Decoupling capacitors are mounted on the PC board.
The DIMMs use optional serial presence detects implemented via a serial E
2
PROM using the two
pin I
2
C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128
bytes of serial PD data are available to the customer.
All 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long space-
saving footprint.
Ordering Information
Type
2k-Refresh:
HYM 64V4005GU-50
HYM 64V4005GU-60
HYM 64V4005GU-70
HYM 72V4005GU-50
HYM 72V4005GU-50
HYM 72V4005GU-70
4k-Refresh:
HYM 64V4045GU-50
HYM 64V4045GU-60
HYM 64V4045GU-70
HYM 72V4045GU-50
HYM 72V4045GU-50
HYM 72V4045GU-70
L-DIM-168-12
L-DIM-168-12
L-DIM-168-12
L-DIM-168-12
L-DIM-168-12
L-DIM-168-12
4M x 64 DRAM module (access time 50 ns)
4M x 64 DRAM module (access time 60 ns)
4M x 64 DRAM module (access time 70 ns)
4M x 72 DRAM module (access time 50 ns)
4M x 72 DRAM module (access time 60 ns)
4M x 72 DRAM module (access time 70 ns)
L-DIM-168-12
L-DIM-168-12
L-DIM-168-12
L-DIM-168-12
L-DIM-168-12
L-DIM-168-12
4M x 64 DRAM module (access time 50 ns)
4M x 64 DRAM module (access time 60 ns)
4M x 64 DRAM module (access time 70 ns)
4M x 72 DRAM module (access time 50 ns)
4M x 72 DRAM module (access time 60 ns)
4M x 72 DRAM module (access time 70 ns)
Ordering
Code
Package
Descriptions
Semiconductor Group
2
HYM 64(72)V4005/45GU-50/-60/-70
4M x 64/72 DRAM Module
Pin Names
A0-A10
A0-A10
A0-A11
A0-A9
DQ0 - DQ63
CB0-CB7
RAS0, RAS2
CAS0 - CAS7
WE0, WE2
OE0, OE2
Vcc
Vss
SCL
SDA
SA0-SA2
N.C.
DU
Row Address Input for HYB64/72V4005
Column Address Input for HYB64/72V4005
Row Address Input for HYB64/72V4045
Column Address Input for HYB64/72V4045
Data Input/Output
Check Bit Data Input/Output ( x72 only)
Row Address Strobe
Column Address Strobe
Read / Write Input
Output Enable
Power (+3.3 Volt)
Ground
Clock for Presence Detect
Serial Data Out for Presence Detect
Serial Presence Detect Addresses
No Connection
Don’t use
Semiconductor Group
3
HYM 64(72)V4005/45GU-50/-60/-70
4M x 64/72 DRAM Module
Pin Configuration
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VCC
WE0
CAS0
CAS1
RAS0
OE0
VSS
A0
A2
A4
A6
A8
A10
NC
VCC
VCC
DU
PIN #
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
VSS
OE2
RAS2
CAS2
CAS3
WE2
VCC
NC
NC
CB3
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
NC
DU
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
NC
NC
NC
SDA
SCL
VCC
PIN #
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Symbol
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VCC
DU
CAS4
CAS5
NC
DU
VSS
A1
A3
A5
A7
A9
A11
NC
VCC
DU
DU
PIN #
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
VSS
DU
NC
CAS6
CAS7
DU
VCC
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
DU
NC
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
NC
NC
SA0
SA1
SA2
VCC
Semiconductor Group
4
HYM 64(72)V4005/45GU-50/-60/-70
4M x 64/72 DRAM Module
RAS0
WE0
OE0
CAS0
DQ0-DQ3
RAS2
WE2
OE2
CAS4
I/O1-I/O4
D0
DQ32-DQ35
I/O1-I/O4
D8
DQ4-DQ7
CAS1
DQ8-DQ11
I/O1-I/O4
D1
D36-DQ39
I/O1-I/O4
D9
CAS5
I/O1-I/O4
D2
DQ40-DQ43
I/O1-I/O4
D10
DQ12-DQ15
I/O1-I/O4
D3
DQ44-DQ47
I/O1-I/O4
D11
CAS2
DQ16-DQ19
I/O1-I/O4
D4
CAS6
DQ48-DQ51
I/O1-I/O4
D12
D20-DQ23
CAS3
DQ24-DQ27
I/O1-I/O4
D5
DQ52-DQ55
CAS7
I/O1-I/O4
D13
I/O1-I/O4
D6
DQ56-DQ59
I/O1-I/O4
D14
DQ28-DQ31
I/O1-I/O4
D7
DQ60-DQ63
I/O1-I/O4
D15
E
2
PROM (256wordx8bit)
A0-A10,(A11)
VCC
D1-D15
C0-C15
VSS
SA0
SA1
SA2
SCL
SDA
4M x 64 DIMM Module Block Diagram
Semiconductor Group
5
