64Mx72 bit SDRAM Registered DIMM H-Series
with PLL & PC/100 SDRAM Specification Supporting
based on 32Mx8 SDRAM, LVTTL, 4-Banks & 8K Refresh
HYM72V75R6431
PRELIMINARY
DESCRIPTION
The HYM72V75R6431 H-Series are high speed 3.3-Volt synchronous dynamic RAM Modules composed
of eighteen 32Mx8 bit Synchronous DRAMs in 54-pin TSOPII, two 48-pin SOP Register Buffers, one 24-pin
SOP PLL and 8-pin TSSOP 2K bit E
2
PROM on a 168-pin glass-epoxy printed circuit board. One 0.22µF and
one 0.0022µF decoupling capacitors per each SDRAM are mounted on the module.
The HYM72V75R6431 H-Series are gold plated socket type Dual In-line Memory Modules suitable for
easy interchange and addition of 512M bytes memory. All addresses, data and control inputs are latched on
the rising edge of the master clock input. The data paths are internally pipelined to achieve very high
bandwidths.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
1.700” (43.18mm) PCB Height
168-Pin Registered DIMM with Double Sided
ECC support
One 0.22µF and one 0.0022µF decoupling
capacitors adopted
Serial Presence Detect with Serial E
2
PROM
Two Register Buffers & one Inverter used
(with PLL)
Supports Flow-through or Register mode by Pin
No. 147 (REGE)
Meets all the other JEDEC specifications
Single 3.3V±0.3V power supply
All device pins are LVTTL compatible
8192 refresh cycles every 64ms
Auto precharge/precharge all banks by A
10
flag
•
Possible to assert random column address
every clock cycle
•
Interleaved auto refresh mode
•
Programmable burst lengths and sequences
- 1,2,4,8,full page for Sequential type
- 1,2,4,8 for Interleave type
•
Programmable /CAS latency ; 2,3 clocks
•
Support clock suspend/power down mode by
CKE0
•
Data mask function by DQM
•
Mode register set programming
•
Burst termination command
•
Self refresh provides minimum power, full
internal refresh control
ORDERING INFORMATION
Part No.
HYM72V75R6431TH-8
HYM72V75R6431TH-10P
HYM72V75R6431TH-10S
Max. Clock
Frequency
Power
PCB
Height
1.700”
Package
Based Comp. Part No
HY57V2578020TC-8
HY57V2578020TC-10P
HY57V2578020TC-10S
125MHz
100MHz
100MHz
Normal
TSOPII
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.0 / Nov.98
HYM72V75R6431 H-Series
PIN DESCRIPTION
Pin
CK0-CK3
CKE0
/S0-/S3
Pin Name
Clock
Clock Enable
Chip Select
Row Address
Strobe, Column
Address
Strobe, Write
Enable
Data Input /
Output Mask
Data Input /
Output
Check bit input
/ output
Bank Address
Address
Power
Supply/Ground
Serial Address
and Data Input /
Output.
Serial Clock
INPUT
Write Protection
Register Buffer
Enable
Description
The system clock input; All other inputs are registered to the SDRAM on the rising
edge of CLK. CK1 – CK3 are not used in this module.
Controls internal clock signal and when deactivated, the SDRAM will be either
one of the states among power down, suspend, or self refresh.
Command input enable of mask except CLK, CKE and DQM
/RAS,
/CAS,/WE
/RAS, /CAS and /WE define the operation.
Refer function truth table for details
DQM0-7
DQ0-DQ63
CB0-CB7
BA0, BA1
A0-A12
Vcc/Vss
SDA
SCL
SA0-SA2
WP
REGE
DQM control output buffer in read mode and masks input data in write mode
Multiplexed data input / output pin
Check bits for ECC
Select either one of banks during both /RAS and /CAS activity
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9,
Auto-precharge flag: A10
Power supply and ground for internal circuit and input buffer
Serial Address and Data Input / Output for EEPROM
Serial Clock
Addresses in Serial E
2
PROM for Socket Presence.
EEPROM Write Protection
When REGE is low, this module will be operated as registered mode.
Rev. 0.0 / Nov.98
2
HYM72V75R6431 H-Series
PIN NAME
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NAME
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
Vss
NC
NC
Vcc
/WE
DQM0
DQM1
/S0
NC
Vss
A0
A2
A4
A6
A8
A10(AP)
BA1
Vcc
Vcc
CK0
#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
NAME
Vss
NC
/S2
DQM2
DQM3
NC
Vcc
NC
NC
CB2
CB3
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
*CK2
NC
WP
SDA
SCL
Vcc
#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
NAME
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
CB4
CB5
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
/S1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
*CK1
A12
#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
NAME
Vss
CKE0
/S3
DQM6
DQM7
NC
Vcc
NC
NC
CB6
CB7
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
REGE
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
*CK3
NC
SA0
SA1
SA2
Vcc
Note : 1. CK1 - CK3 are connected with termination R/C (Refer to the block diagram)
Rev. 0.0 / Nov. 98
3
HYM72V75R6431 H-Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10 Ohms.
2. The padding capacitances of termination R/C for CK1-3 are 12 pF.
Rev. 0.0 / Nov.98
4
HYM72V75R6431 H-Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
BYTE12
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
BYTE36 -
61
BYTE62
BYTE63
BYTE64
BYTE65 -
71
BYTE72
FUNCTION
DESCRIBED
# of Bytes Written into Serial Memory
at Module Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @ /CAS Latency=3
Access Time from Clock @ /CAS Latency=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back Random Column
Address
Burst Lengths Supported
# of Banks on SDRAM Device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
SDRAM Module Attributes, General
SDRAM Cycle Time @ /CAS Latency=2
Access Time from Clock @ /CAS Latency=2
SDRAM Cycle Time @ /CAS Latency=1
Access Time from Clock @ /CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse width (tRAS)
Module Bank Density
Command & Address signal input setup time (tAS)
Command & Address signal input hold time (tAH)
Data signal input setup time (tDS)
Data signal input hold time (tDH)
Superset Information(May be used in the future)
SPD Revision
Checksum for Byte 0-62
Manufacturer JEDEC ID Code
Manufacturer JEDEC ID Code
-
2ns
1ns
2ns
1ns
8ns
6ns
FUNCTION
-8
-10P
128 Bytes
256 Bytes
SDRAM
13
10
2 Banks
72 Bits
-
LVTTL
10ns
6ns
ECC
7.8125µs
/ Self Refresh Supported
X8
X8
tCCD=1 Latency
1,2,4,8,Full Page
4 Banks
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Neither Buffered nor Registered
+/-10% voltage tolerance, Burst
read, Single bit write, Precharge
all, Auto precharge,
10ns
6ns
-
-
20ns
16ns
20ns
48ns
10ns
6ns
-
-
20ns
20ns
20ns
50ns
256MB
2ns
1ns
2ns
1ns
-
Intel SPD 1.2A
-
Hyundai JEDEC ID
Unused
HEI (Korea)
HEA (United States)
HEU (Europe)
-
3Ch
2ns
1ns
2ns
1ns
20h
10h
20h
10h
12ns
6ns
-
-
20ns
20ns
20ns
50ns
A0h
60h
00h
00h
14h
10h
14h
30h
10ns
6ns
80h
60h
-10S
-8
VALUE
-10P
80h
08h
04h
0Dh
0Ah
02h
48h
00h
01h
A0h
60h
02h
82h
08h
08h
01h
8Fh
04h
06h
01h
01h
16h
0Eh
A0h
60h
00h
00h
14h
14h
14h
32h
40h
20h
10h
20h
10h
00h
12h
62h
ADh
FFh
01h
02h
03h
82h
4, 5
20h
10h
20h
10h
C0h
60h
00h
00h
14h
14h
14h
32h
2
A0h
60h
1
-10S
NOTE
Manufacturing Location
Rev. 0.0 / Nov. 98
5
FPGA/CPLD
