200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb 1st ver.
This Hynix unbuffered Slim Outline Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. DDR2
SDRAMs in Fine Ball Grid Array(FBGA) packages on a 200pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based
Unbuffered DDR2 SO-DIMM series provide a high performance 8 byte interface in 67.60mm width form factor of indus-
try standard. It is suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2 Synchronous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
All inputs and outputs are compatible with SSTL_1.8
interface
Posted CAS
Programmable CAS Latency 3 ,4 ,5
OCD (Off-Chip Driver Impedance Adjustment) and
ODT (On-Die Termination)
Fully differential clock operations (CK & CK)
•
•
•
•
•
•
•
Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball(x8), 84ball(x16)
FBGA
67.60 x 30.00 mm form factor
Lead-free Products are RoHS compliant
•
•
•
•
•
ORDERING INFORMATION
Part Name
HYMP532S646-E3/C4
HYMP564S648-E3/C4
HYMP564S646-E3/C4
HYMP112S64M8-E3/C4
HYMP532S64P6-E3/C4
HYMP564S64P8-E3/C4
HYMP564S64P6-E3/C4
HYMP112S64MP8-E3/C4
Density
256MB
512MB
512MB
1GB
256MB
512MB
512MB
1GB
Organization
32Mx64
64Mx64
64Mx64
128Mx64
32Mx64
64Mx64
64Mx64
128Mx64
# of
DRAMs
4
8
8
16
4
8
8
16
# of
ranks
1
1
2
2
1
1
2
2
Materials
Leaded
Leaded
Leaded
Leaded
Lead free
Lead free
Lead free
Lead free
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Feb. 2005
1
1200pin
Unbuffered DDR2 SDRAM SO-DIMMs
SPEED GRADE & KEY PARAMETERS
E3 (DDR2-400)
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
400
-
3-3-3
C4 (DDR2-533)
400
533
-
4-4-4
Unit
Mbps
Mbps
Mbps
tCK
ADDRESS TABLE
Density
256MB
512MB
512MB
1GB
Organization Ranks
32M x 64
64M x 64
64M x 64
128M x 64
1
2
1
2
SDRAMs
32Mb x 16
64Mb x 8
32Mb x 16
64Mb x 8
# of
DRAMs
4
8
8
16
# of row/bank/column Address
13(A0~A12)/2(BA0~BA1)/10(A0~A9)
14(A0~A13)/2(BA0~BA1)/10(A0~A9)
13(A0~A12)/2(BA0~BA1)/10(A0~A9)
14(A0~A13)/2(BA0~BA1)/10(A0~A9)
Refresh
Method
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
Rev. 1.0 / Feb. 2005
2
1200pin
Unbuffered DDR2 SDRAM SO-DIMMs
PIN DESCRIPTION
Symbol
Type
Polarity
Cross
Point
Pin Description
The system clock inputs. All adress an commands lines are sampled on the cross point of
the rising edge of CK and falling edge of CK. A Delay Locked Loop(DLL) circuit is driven
from the clock inputs and output timing for read operations is synchronized to the input
clock.
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the com-
mand decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by
S1
When sampled at the cross point of the rising edge of CK and falling edge of CK, CAS, RAS
and WE define the operation to be excecuted by the SDRAM.
Selects which DDR2 SDRAM internal bank of four is activated.
Active
High
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
During a Bank Activate command cycle, difines the row address when sampled at the cross
point of the rising edge of CK and falling edge of CK. During a Read or Write command
cycle, defines the column address when sampled at the cross point of the rising edge of CK
and falling edge of CK. In addition to the column address, AP is used to invoke autopre-
charge operation at the end of the burst read or write cycle. If AP is high., autoprecharge
is selected and BA0-BAn defines the bank to be precharged. If AP is low, autoprecharge is
disabled. During a Precharge command cycle., AP is used in conjunction with BA0-BAn to
control which bank(s) to precharge. If AP is high, all banks will be precharged regardless
of the state of BA0-BAn inputs. If AP is low, then BA0-BAn are used to define which bank
to precharge.
Data Input/Output pins.
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if
it is high. In Read mode, DM lines have no effect.
The data strobe, associated with one data byte, sourced whit data transfers. In Write
mode, the data strobe is sourced by the controller and is centered in the data window. In
Read mode, the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge
of the data window. DQS signals are complements, and timing is relative to the crosspoint
of respective DQS and DQS. If the module is to be operated in single ended strobe mode,
all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers
programmed approriately.
Power supplies for core, I/O, Serial Presense Detect, and ground for the module.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister
must be connected to V
DD t
o act as a pull up.
This signals is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from SCL to VDD to act as a pull up.
Address pins used to select the Serial Presence Detect base address.
The TEST pin is reserved for bus analysis tools and is not connected on normal memory
modules(SODIMMs).
CK[1:0], CK[1:0]
Input
CKE[1:0]
Input
Active
High
S[1:0]
Input
Active
Low
Active
Low
RAS, CAS, WE
BA[1:0]
ODT[1:0]
Input
Input
Input
A[9:0], A10/AP,
A[15:11]
Input
DQ[63:0]
DM[7:0]
In/Out
Input
DQS[7:0], DQS[7:0] In/Out
Cross
point
V
DD
, V
DD
SPD,V
SS
SDA
SCL
SA[1:0]
TEST
Supply
In/Out
Input
Input
In/Out
Rev. 1.0 / Feb. 2005
3
1200pin
Unbuffered DDR2 SDRAM SO-DIMMs
PIN ASSIGNMENT
Pin
NO.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Front
Side
VREF
VSS
DQ0
DQ1
VSS
DQS0
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2
Pin
NO.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Back
Side
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
Pin
NO.
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
Front
Side
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
Pin
NO.
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
Back
Side
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3
DQS3
VSS
DQ30
DQ31
VSS
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
Pin
NO.
101
103
105
107
109
111
113
115
117
121
123
125
127
131
133
135
137
139
141
143
145
147
149
Front
Side
A1
VDD
A10/AP
BA0
WE
VDD
CAS
NC/S1
VDD
VSS
DQ32
DQ33
VSS
DQS4
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
Pin
NO.
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Back
Side
A0
VDD
BA1
RAS
S0
VDD
ODT0
A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5
DQS5
VSS
Pin
NO.
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
Front
Side
DQ42
DQ43
VSS
DQ48
DQ49
VSS
VSS
DQS6
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
Pin
NO.
152
154
156
158
160
162
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Back
Side
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
NC,TEST 164
119 NC/ODT1
NC/CKE1 129
Pin Location
2
40
42
200
Front
1
39 41
199
Back
Rev. 1.0 / Feb. 2005
4
1200pin
Unbuffered DDR2 SDRAM SO-DIMMs
FUNCTIONAL BLOCK DIAGRAM
256MB(32Mbx64) : HYMP532S646-E3/C4
/S 1
N .C .
O D T1
N .C .
3
Ω + /−
5 %
CKE0
ODT0
/S 0
CKE1
N .C .
DQS0
/D Q S 0
DM0
LDQS
/U D Q S
LDM
/C S
ODT
CKE
DQS4
/D Q S 4
DM4
LDQS
/L D Q S
LDM
/C S
ODT
CKE
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I /O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
/D Q S 5
DM5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
/C S
ODT
CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D2
DQS1
/D Q S 1
DM1
DQ8
DQ8
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ15
UDQS
/U D Q S
UDM
UDQS
/U D Q S
UDM
I/O 8
I/O 9
I/O 1 0
I/O 1 1
I/O 1 2
I/O 1 3
I/O 1 4
I /O 1 5
I/O 8
I/O 9
I/O 1 0
I/O 1 1
I/O 1 2
I/O 1 3
I/O 1 4
I /O 1 5
DQS2
/D Q S 2
DM2
LDQS
/L D Q S
LDM
DQS6
/D Q S 6
DM6
LDQS
/L D Q S
LDM
/C S
ODT
CKE
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQS3
/D Q S 3
DM3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
/U D Q S
UDM
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQS7
/D Q S 7
DM7
D3
UDQS
/U D Q S
UDM
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
I/O 8
I/O 9
I /O 1 0
I /O 1 1
I /O 1 2
I /O 1 3
I /O 1 4
I/O 1 5
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
I /O 8
I /O 9
I/O 1 0
I/O 1 1
I/O 1 2
I/O 1 3
I/O 1 4
I/ O 1 5
3
Ω
+ /- 5 %
B A 0 -B A 1
A 0 -A N
/R A S
/C A S
/W E
SCL
SDRAMS
SDRAMS
SDRAMS
SDRAMS
SDRAMS
D 0 -3
D 0 -3
D 0 -3
D 0 -3
D 0 -3
SA0
SA1
SCL
A0
A1
A2
SDA
S e r ia l P D
WP
SDA
V
DD
SP D
CK0
2 lo a d s
S e r ia l P D
S D R A M S D O -D 3
V
REF
V
DD
/C K 0
S D R A M S D O -D 3 , V D D a n d V D D Q
S D R A M S D O -D 3 , S P D
CK1
2 lo a d s
V
SS
/C K 1
N o te s :
1 . R e s is to r v a lu e s a r e 2 2 O h m + /- 5 %
Rev. 1.0 / Feb. 2005
5
