Aug 2008
HYS72T128501EFD–3S–C2
HYS72T[256/512]4[20/21]EFD–3S–C2
HYS72T[256/512]5[20/21/40]EFD–3S–C2
HYS72T[256/512]5[20/21/40]EFD–25FC2
240-Pin Fully-Buffered DDR2 SDRAM Modules
DDR2 SDRAM
EU RoHS Compliant Products
Advance
Internet Data Sheet
Rev.0.90
Advance Internet Data Sheet
HYS72T[128/256/512][4/5][01/20/21/40]EFD–[25F/3S]C2
Fully-Buffered DDR2 SDRAM Modules
Revision History: Rev.0.90, 2008-08-14
Page 6
Page 23
Updated
“Ordering Information” on Page 6
Updated
“SPD Codes” on Page 23
Previous Revision: Rev. 0.80, 2007-08-24
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qag_techdoc_A4, 4.20, 2008-01-25
01102008-519I-QT9G
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Advance Internet Data Sheet
HYS72T[128/256/512][4/5][01/20/21/40]EFD–[25F/3S]C2
Fully-Buffered DDR2 SDRAM Modules
General Use Restriction
This document as well as any and all information, products,
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Qimonda grants you the limited right to use the Materials for
the sole purpose of evaluating the products of Qimonda
("Products") to the extent this evaluation is related to your
(potential) purchase of such Products. You agree not to use
the Materials for any other purpose without the prior written
consent of Qimonda. Without limitation, you agree not to
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that, you have no right to modify, edit, alter or enhance any of
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THE MATERIALS ARE PROVIDED BY QIMONDA ON AN
AS IS BASIS, AND QIMONDA EXPRESSLY DISCLAIMS
ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED,
INCLUDING WITHOUT LIMITATION WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE, WITH RESPECT TO ANY MATERIALS.”
Rev.0.90, 2008-08-14
01102008-519I-QT9G
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Advance Internet Data Sheet
HYS72T[128/256/512][4/5][01/20/21/40]EFD–[25F/3S]C2
Fully-Buffered DDR2 SDRAM Modules
1
1.1
Overview
Features
• Detects errors on the channel and reports them to the host
memory controller.
• Automatic DDR2 DRAM Bus Calibration.
• Automatic Channel Calibration.
• Full Host Control of the DDR2 DRAMs.
• Over-Temperature Detection and Alert.
• Hot Add-on and Hot Remove Capability.
• MBIST and IBIST Test Functions.
• Transparent Mode for DRAM Test Support.
• Low profile: 133.35 mm x 30.35 mm
• 240 Pin gold plated card connector with 1.00mm contact
centers (industry standard pending).
• Based on industry standard reference card designs
(industry standard pending).
• SPD (Serial Presence Detect) with 256 Byte serial
E
2
PROM.Performance.
• RoHS Compliant Products
1)
This chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.
• 240-pin Fully-Buffered ECC Dual-In-Line DDR2 SDRAM
Module for PC, Workstation and Server main memory
applications.
• One rank 128M
×
72 , two rank 256M
×
72, 512M
×
72 and
four rank 512M
×
72 module organization, and 128M
×
8,
256M
×
4 chip organization.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
• 4GB, 2GB, 1GB Modules built with chipsize packages PG-
TFBGA-60.
• Re-drive and re-sync of all address, command, clock and
data signals using AMB (Advanced Memory Buffer).
• High-Speed Differential Point-to-Point Link Interface at
1.5 V (industry standard pending).
• Host Interface and AMB component industry standard
compliant.
• Supports SMBus protocol interface for access to the AMB
configuration registers.
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
CL3
CL5
CL4
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
–25F
DDR2–800D
PC2–6400D
5–5–5
–3S
DDR2–667D
PC2–5300D
5–5–5
200
333
266
15
15
45
60
Unit
t
CK
MHz
MHz
MHz
ns
ns
ns
ns
f
CK3
f
CK5
f
CK4
t
RCD
t
RP
t
RAS
t
RC
200
400
266
12.5
12.5
45
57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev.0.90, 2008-08-14
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Advance Internet Data Sheet
HYS72T[128/256/512][4/5][01/20/21/40]EFD–[25F/3S]C2
Fully-Buffered DDR2 SDRAM Modules
1.2
Description
data in- and output. The AMB communicates with the host
controller and / or the adjacent DIMMs on a system board
using an Industry Standard High-Speed Differential Point-to-
Point Link Interface at 1.5 V.
The Advanced Memory Buffer also allows buffering of
memory traffic to support large memory capacities. All
memory control for the DRAM resides in the host, including
memory request initiation, timing, refresh, scrubbing, sparing,
configuration access, and power management. The
Advanced Memory Buffer interface is responsible for handling
channel and memory requests to and from the local DIMM
and for forwarding requests to other DIMMs on the memory
channel. Fully Buffered DIMM provides a high memory
bandwidth, large capacity channel solution that has a narrow
host interface. The maximum memory capacity is 288 DDR2
SDRAM devices per channel or 8 DIMMs.
This document describes the electrical and mechanical
features of a 240-pin, PC2-5300F and PC2-6400F ECC type,
Fully Buffered Double-Data-Rate Two Synchronous DRAM
Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs).
Fully Buffered DIMMs use commodity DRAMs isolated from
the memory channel behind a buffer on the DIMM. They are
intended for use as main memory when installed in systems
such as servers and workstations. PC2-5300F and PC2-
6400F refers to the DIMM naming convention indicating the
DDR2 SDRAMs running at 333 respectively 400 MHz clock
speed and offering 5300 resp. 6400 Mb/s peak bandwidth.
FB-DIMM features a novel architecture including the
Advanced Memory Buffer. This single chip component,
located in the center of each DIMM, acts as a repeater and
buffer for all signals and commands which are exchanged
between the host controller and the DDR2 SDRAMs including
Rev.0.90, 2008-08-14
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