Production
March 2003
®
P1818/19/20/21/22
Low Power Mobile VGA EMI Reduction IC
Features
•
•
•
•
FCC approved method of EMI attenuation
Provides up to 15 dB EMI reduction
Generates a low EMI spread spectrum clock and a
non-spread reference clock of the input frequency
Optimized for frequency range from 10 MHz to 160
MHz
P1818: 10 to 20 MHz
P1819: 20 to 40 MHz
P1820: 40 to 80 MHz
P1821: 10 to 40 MHz
P1822: 80 to 160 MHz
Internal loop filter minimizes external components
and board space
•
•
•
•
•
•
•
•
•
•
Selectable spread options: Down Spread and Cen-
ter Spread
Low inherent cycle-to-cycle jitter
Eight spread % selections: +/-0.625% to –3.5%
3.3V operating voltage
CMOS/TTL compatible inputs and outputs
Low power CMOS design
Supports notebook VGA and other LCD timing
controller applications
Power down function for mobile application
Products are available for industrial temperature
range.
Available in 8-pin SOIC and TSSOP
•
Product Description
The P18xx is a versatile spread spectrum frequency
modulator designed specifically for a wide range of input
clock frequencies from 10 to 160 MHz (see Input Fre-
quency and Modulation Rate Selections). The P18xx
can generate an EMI reduced clock from crystal,
ceramic resonator, or system clock. The P18xx-A to
P18xx-H offer various combinations of spread options
and percentage deviations (see Spread Deviation Selec-
tions). These combinations include Down Spread,
Center Spread and percentage deviation range from
±0.625% to -3.50%.
The P18xx reduces electromagnetic interference (EMI)
at the clock source, allowing a system wide EMI
reduction for all the down stream clocks and data
dependent signals. The P18xx allows significant system
cost savings by reducing the number of circuit board
layers, ferrite beads, shielding, and other passive
components that are traditionally required to pass EMI
regulations.
The P18xx modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock,
thereby decreasing the peak amplitudes of its
harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal
produced by oscillators and most clock generators.
Lowering EMI by increasing a signal’s bandwidth is
called “spread spectrum clock generation”.
The P18xx uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all-digital method.
Applications
The P18xx is targeted toward EMI management for
memory and LVDS interfaces in mobile graphic
chipsets and high-speed digital applications such as
PC peripheral devices, consumer electronics, and
embedded controller systems.
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA 95054 • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
P1818/19/20/21/22
®
Pin Diagrams
X IN 1
VSS
SRS
M odO ut
2
3
4
P 1 8 2 1 A /B /C /D
X IN 1
VSS
SRS
M odO ut
2
3
4
P 1 8 1 8 A /B /C /D
P 1 8 1 9 A /B /C /D
P 1 8 2 0 A /B /C /D
8
7
6
5
XOUT
VDD
PD#
REF
8
7
6
5
XOUT
VDD
FRS
REF
X IN 1
VSS
D_C
M odO ut
2
3
4
P 1 8 1 8 E /F /G /H
P 1 8 1 9 E /F /G /H
P 1 8 2 0 E /F /G /H
8
7
6
5
XOUT
VDD
PD#
REF
X IN 1
VSS
SRS
M odO ut
2
3
4
P1822A
8
7
6
5
MRS
VDD
SSON#
SR0
Block Diagram
D_C PD# MRS FRS SRS
VDD
Modulation
XIN
XOUT
Feedback
Divider
Crystal
Oscillator
Frequency
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
REF
P1818/19/20/21/22 Block Diagram
VSS
March 2003
Low Power Mobile VGA EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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P1818/19/20/21/22
®
Input Frequency and Modulation Rate
Part number
P1818
P1819
P1820
FRS=0
P1821
P1822
FRS=1
Input
frequency range
10 MHz to 20 MHz
20 MHz to 40 MHz
40 MHz to 80 MHz
10 MHz to 20 MHz
20 MHz to 40 MHz
80 MHz to 160 MHz
Output
frequency range
10 MHz to 20 MHz
20 MHz to 40 MHz
40 MHz to 80 MHz
10 MHz to 20 MHz
20 MHz to 40 MHz
80 MHz to 160 MHz
Modulation rate
Input frequency / 256
Input frequency / 512
Input frequency / 2048
Input frequency / 256
Input frequency / 512
Input frequency / 3584
Spread Deviation Selections
Part number
1
P1818
2
/19/20/21A
P1818/19/20/21B
P1818/19/20/21C
P1818/19/20/21D
P1818/19/20E
P1818/19/20F
P1818/19/20G
P1818
2
/19/20H
SRS
0
1
0
1
0
1
0
1
N/A
N/A
N/A
N/A
0
0
1
1
0
0
1
1
SR0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
0
1
0
1
0
1
D_C
N/A
N/A
N/A
N/A
0
1
0
1
0
1
0
1
N/A
Spread deviation
-2.50% (Down)
-3.50% (Down)
-1.25% (Down)
-1.75% (Down)
+/-1.25% (Center)
+/-1.75% (Center)
+/-0.625% (Center)
+/-0.875% (Center)
-1.25% (Down)
+/-0.625% (Center)
-2.5% (Down)
+/-1.25% (Center)
-1.75% (Down)
+/-0.875% (Center)
-3.5% (Down)
+/-1.75% (Center)
-1.25% (Down)
-2.50% (Down)
-1.75% (Down)
-3.50% (Down)
+/-0.625% (Center)
+/-1.25% (Center)
+/-0.875% (Center)
+/-1.75% (Center)
P1822A
N/A
P1822B
1.
A
through
H
represents various combinations of spread deviations, options, and modulation rates.
2. Refer to Frequency vs. Deviation (P1818A and P1818H).
March 2003
Low Power Mobile VGA EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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P1818/19/20/21/22
®
Frequency vs. Deviation (P1818A and P1818H)
Deviation in P1818A
Frequency
SRS = 1
10 MHz
15 MHz
20 MHz
-4.4%
-1.8%
-0.8%
SRS = 0
-3.3%
-1.26%
-0.6%
D_C = 1
-4.4%
-1.8%
-0.8%
D_C = 0
±2.2%
±0.9%
±0.4%
Deviation in P1818H
Pin Description
Pin
number
1
2
3
Name
XIN
VSS
SRS
Type
I
P
I
Description
Connect to externally generated clock signal or crystal.
Ground Connection. Connect to system ground.
Spread Range Select. Digital logic input used to select frequency devi-
ation (see Spread Deviation Selections). This pin has an internal pull-
up resistor.
Digital logic input used to select Down (LOW) or Center (HIGH) Spread
Options (see Spread Deviation Selections). This pin has an internal
pull-up resistor.
Spread Spectrum clock output (see Input Frequency and Modulation
Rate Selections and Spread Deviation Selections).
Non-modulated reference output clock of the input frequency.
Frequency Range Select. Digital logic input used to select input fre-
quency range (see Input Frequency and Modulation Rate Selections).
This pin has an internal pull-up resistor.
Power-Down control pin. Pull LOW to enable Power-Down mode. This
pin has an internal pull-up resistor.
Connect to +3.3V
Connect to crystal. No connect if externally generated clock signal is
used.
Modulation Rate Select. Digital logic input used to select Modulation
Rate (see Spread Deviation Selections). This pin has an internal pull-
up resistor.
3
1
D_C
I
4
5
5/6
1
ModOut
REF
FRS
O
O
I
6
1
7
8
8
1
PD#
VDD
XOUT
MRS
I
P
I
I
1. Please refer to Figure 1 for pin assignment.
March 2003
Low Power Mobile VGA EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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P1818/19/20/21/22
®
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
Parameter
Voltage on any pin with respect to GND
Storage temperature
Operating temperature
Rating
-0.5 to +7.0
-65 to +125
0 to +70
Unit
V
ºC
ºC
DC Electrical Characteristics
3.3 V, 25° C
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
Parameter
Input low voltage
Input high voltage
Input low current (inputs D_C,
PD#, MRS, FRS, SRS)
Input high current
XOUT output low current
(@ 0.4 V, V
DD
= 3.3 V)
XOUT output high current
(@ 2.5 V, V
DD
= 3.3 V)
Output low voltage
(V
DD
=3.3 V, I
OL
= 20 mA)
Output high voltage
(V
DD
=3.3 V, I
OH
= 20 mA)
Static supply current
Standby mode
Dynamic supply current
Normal mode (3.3 V and 25 pF
probe loading)
Operating voltage
Power up time
(first locked clock cycle after
power up)
Clock output impedance
Min
GND – 0.3
2.00
-60.0
–
2.00
–
–
–
–
7.1
f
IN-min
–
–
3.3
0.18
Typ
–
–
–
–
–
–
–
–
4.5
–
Max
0.8
V
DD
+ 0.3
-20.00
1.00
12.00
12.00
0.4
2.8
–
26.9
f
IN-max
–
–
V
mS
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
DD
t
ON
Z
OUT
–
50
–
Ω
March 2003
Low Power Mobile VGA EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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