.
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Features
• High Performance:
-68 -75A, -260, -360, -10,
Units
CL=3 CL=3 CL=2 CL=3 CL=3
f
CK
Clock Frequency
t
CK
Clock Cycle
t
AC
Clock Access Time
1
t
AC
Clock Access Time
2
150
6.67
6
133
7.5
—
5.4
100
10
—
6
100
10
—
6
100
10
7
9
MHz
ns
ns
ns
• Programmable Wrap: Sequential or Interleave
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard or Low Power operation
• 4096 refresh cycles/64ms
• Random Column Address every CLK (1-N Rule)
• Single 3.3V
±
0.3V Power Supply
• LVTTL compatible
• Package: 54-pin 400 mil TSOP-Type II
2 High Stack TSOJ
—
1. Terminated load. See AC Characteristics on page 41.
2. Unterminated load. See AC Characteristics on page 41.
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by A12/A13 (Bank Select)
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, full-page
Description
The IBM0364404, IBM0364804, and IBM0364164
are four-bank Synchronous DRAMs organized as
4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and
1Mbit x 16 I/O x 4 Bank, respectively. IBM03644B4,
a stacked version of the x4 component, is also
offered. These synchronous devices achieve high-
speed data transfer rates of up to 150MHz by
employing a pipeline chip architecture that synchro-
nizes the output data to a system clock. The chip is
fabricated with IBM’s advanced 64Mbit single tran-
sistor CMOS DRAM process technology.
The device is designed to comply with all JEDEC
standards set for synchronous DRAM products,
both electrically and mechanically. All of the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CLK). Internal chip operating modes
are defined by combinations of these signals and a
command decoder initiates the necessary timings
for each operation. A fourteen bit address bus
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
and two bank select addresses (A12, A13) are
strobed with RAS. Ten column addresses (A0-A9)
plus bank select addresses and A10 are strobed
with CAS. Column address A9 is dropped on the x8
device and column addresses A8 and A9 are
dropped on the x16 device. Access to the lower or
upper DRAM in a stacked device is controlled by
CS0 and CS1, respectively.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A9
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 150MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Simultaneous opera-
tion of both decks of a stacked device is allowed,
depending on the operation being done. Auto
Refresh (CBR), Self Refresh, and Low Power opera-
tion are supported.
19L3265.E35856B
01/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Pin Assignments for Planar Components
(Top View)
V
DD
DQ0
V
DDQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
DDQ
DQ5
DQ6
V
SSQ
DQ7
V
DD
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
V
DD
NC
V
DDQ
NC
DQ0
V
SSQ
NC
NC
V
DDQ
NC
DQ1
V
SSQ
NC
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
NC
V
SSQ
NC
DQ3
V
DDQ
NC
NC
V
SSQ
NC
DQ2
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ11
V
SSQ
DQ10
DQ9
V
DDQ
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
NC
LDQM
NC
WE
WE
WE
CAS
CAS
CAS
RAS
RAS
RAS
CS
CS
CS
A13/BS0 A13/BS0 A13/BS0
A12/BS1 A12/BS1 A12/BS1
A10/AP A10/AP
A10/AP
A0
A0
A0
A1
A2
A3
V
DD
A1
A2
A3
V
DD
A1
A2
A3
V
DD
54-pin Plastic TSOP(II) 400 mil
4Mbit x 4 I/O x 4 Bank
IBM0364404
2Mbit x 8 I/O x 4 Bank
IBM0364804
1Mbit x 16 I/O x 4 Bank
IBM0364164
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3265.E35856B
01/00
Page 2 of 73
.
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Pin Assignments for 2 High Stack Package (Dual CS Pin)
(Top View)
V
DD
NC
V
DDQ
NC
DQ0
V
SSQ
NC
NC
V
DDQ
NC
DQ1
V
SSQ
NC
V
DD
NC
WE
CAS
RAS
CS0/NC
A13/BS0
A12/BS1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
NC
V
SSQ
NC
DQ3
V
DDQ
NC
NC
V
SSQ
NC
DQ2
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC/CS1
A11
A9
A8
A7
A6
A5
A4
V
SS
54-pin Plastic TSOJ(II) 400 mil
(4Mbit x 4 I/O x 4 Bank) x 2High
IBM03644B4
*
CS0 selects the lower DRAM in the stack.
*
CS1 selects the upper DRAM in the stack.
19L3265.E35856B
01/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Pin Description
CLK
CKE
CS (CS0, CS1)
RAS
CAS
WE
BS1, BS0 (A12, A13)
A0 - A11
Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Bank Select
Address Inputs
DQ0-DQ15
DQM, LDQM, UDQM
V
DD
V
SS
V
DDQ
V
SSQ
NC
—
Data Input/Output
Data Mask
Power (+3.3V)
Ground
Power for DQs (+3.3V)
Ground for DQs
No Connection
—
Input/Output Functional Description
Symbol
CLK
CKE
CS, CS0,
CS1
RAS, CAS,
WE
BS1, BS0
(A12, A13)
Type
Input
Input
Polarity
Positive
Edge
Active
High
Function
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
Input
CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables the
Active Low command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
Active Low
—
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to
be executed by the SDRAM.
Selects which bank is to be active.
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sam-
pled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when
sampled at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If
A10 is low, then BS0 and BS1 are used to define which bank to precharge.
Data Input/Output pins operate in the same manner as on conventional DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high.
In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively.
In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an out-
put enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode,
DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is
low but blocks the write operation if DQM is high.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise immunity.
Input
Input
A0 - A11
Input
—
DQ0 - DQ15
Input-
Output
—
DQM
LDQM
UDQM
Input
Active
High
V
DD
, V
SS
V
DDQ
V
SSQ
Supply
Supply
—
—
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3265.E35856B
01/00
Page 4 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Ordering Information - Planar Devices
(Single CS Pin)
Part Number
IBM
IBM0364404CT3C-75A
IBM0364404CT3C-260
IBM0364404CT3C-360
IBM0364404CT3C-10
IBM0364804CT3C-75A
IBM0364804CT3C-260
IBM0364804CT3C-360
IBM0364804CT3C-10
IBM0364164CT3C-68
IBM0364164CT3C-260
IBM0364164CT3C-360
IBM0364164CT3C-10
IBM0364804PT3C-260
IBM0364804PT3C-360
IBM0364804PT3C-10
IBM0364164PT3C-260
IBM0364164PT3C-360
IBM0364164PT3C-10
1. Part numbers manufactured by an IBM licensee and functionally equivalent to IBM parts.
2. SP: Standard Power; LP: Low Power.
2, 3
3.3V
10ns
400mil
Type II TSOP-54
LP
x16
2, 3
3.3V
10ns
400mil
Type II TSOP-54
LP
x8
IBMN364164CT3C-360
2, 3
IBMN364164CT3C-68
3
3.3V
10ns
6.67ns
400mil
Type II TSOP-54
SP
x16
IBMN364804CT3C-75A
IBMN364804CT3C-260
IBMN364804CT3C-360
2, 3
3
3.3V
10ns
7.5ns
400mil
Type II TSOP-54
SP
x8
Licensee
1
CAS
Latencies
3
Power
Supply
Clock
Cycle
7.5ns
Package
Power
2
Org.
IBMN364404CT3C-75A
IBMN364404CT3C-260
3.3V
IBMN364404CT3C-360
2, 3
10ns
400mil
Type II TSOP-54
SP
x4
Ordering Information - 2 High Stacked Devices
(Dual CS Pin)
Part Number
IBM03644B4CT3C-75A
IBM03644B4CT3C-260
2, 3
IBM03644B4CT3C-360
1. SP: Standard Power.
CAS Latencies
3
3.3V
10ns
Power Supply
Clock Cycle
7.5ns
400mil Type II TSOJ-54
SP
x4
Package
Power
1
Org.
19L3265.E35856B
01/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 73
