IBM043614PQK32K x 36Burst (PowerPC), TQFP package.
Preliminary
Features
• 64K x 18 Organization
• 0.5µ CMOS Technology
• Synchronous Burst Mode of Operation Compati-
ble with i486
TM
and Pentium
TM
Processors
• Supports Pentium
TM
Processor Address
Pipelining
• Common I/O and Registered Outputs
• Single +3.3V
±
5% Power Supply and Ground
• LVTTL I/O Compatible
• Fast OE times: 4, 5ns
IBM041813PQK
64K X 18 BURST PIPELINE SRAM
• Registered Addresses, Data Ins, Control sig-
nals, and Outputs
• Asynchronous Output Enable
• Self-Timed Write Operation and Byte Write
Capability
• Low Power Dissipation
- 1.3 W Active at 100MHz
- 90 mW Standby
• 100 Pin Thin Quad Flat Pack Package
• 5V Tolerant I/O
Description
IBM Microelectronics 1M SRAM is a Synchronous
Burstable Pipelined, high performance CMOS Static
RAM that is versatile, wide I/O, and achieves 4 nsec
access. A single clock is used to initiate the
read/write operation and all internal operations are
self-timed. At the rising edge of the Clock, all
Addresses, Data Ins and Control Signals are regis-
tered internally. Burst mode operation, compatible
with the i486
TM
and Pentium
TM
Processor’s
sequence, is accomplished by integrating input reg-
isters, internal 2-bit burst counter and high speed
SRAM in a single chip. Burst reads are initiated with
either ADSP or ADSC being LOW with a valid
address during the rising edge of clock. Data from
this address plus the three subsequent addresses
will be output. The chip is operated with a single
+3.3 V power supply and is compatible with LVTTL
I/O interfaces.
50H5206
SA14-4665-01
Revised 3/96
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 14
IBM041813PQK
64K X 18 BURST PIPELINE SRAM
Preliminary
X18 TQFP Pin Array Layout
ADSC
ADSP
WEb
WEa
VDD
ADV
83
VSS
CS2
CLK
CS2
OE
NC
NC
NC
CS
NC
A6
A7
A8
82
A9
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
NC
NC
NC
NC
NC
NC
NC
DQ9
DQ10
VSS
VDDQ
DQ11
DQ12
NC
VDD
NC
VSS
DQ13
DQ14
VDDQ
VSS
DQ15
DQ16
DQP2
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
84
A10
NC
NC
NC
NC
NC
DQP1
DQ8
DQ7
VSS
VDDQ
DQ6
DQ5
VSS
NC
VDD
NC
DQ4
DQ3
VDDQ
VSS
DQ2
DQ1
NC
NC
NC
NC
NC
NC
NC
VDD
VSS
A15
A14
A13
A12
A11
NC
NC
NC
NC
NC
NC
Pin Description
A0-A15
DQa - DQb
CLK
WEa
WEb
OE
Address input
Data Input/Output (1-8 , 9-16)
Clock
Write Enable, Byte a (1 to 8 & DQP1)
Write Enable, Byte b (9 to 16 & DQP2)
Output Enable
Chip Selects
Parity bits for byte a, and byte b.
ADSP
ADSC
ADV
CS
V
DD
V
SS
V
DDQ
NC
Address Status Processor
Address status controller
Burst Advance Control
ADSP - Gated Chip Select
Power Supply (+3.3V)
Ground
Output Power Supply (+3.3V)
No Connect
CS2
,
CS2
DQP1,DQP2
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
NC
A5
A4
A3
A2
A1
A0
50H5206
SA14-4665-01
Revised 3/96
Page 2 of 14
Preliminary
IBM041813PQK
64K X 18 BURST PIPELINE SRAM
Block Diagram
Row
Address
A0 - A15
Register
A2 - A9
DQ0 - DQ8
Register
Address
Register
64K x 18 Array
Column
A10 - A15
Register
DQ9 - DQ17
CLK
ADV
SA0
Burst
Binary
Counter
A0
SA1
ADSC
Clear
A1
ADSP
CS
CS
CS2
CS2
Select
Registers
Select
Pipeline
Register
WEa
Byte
Write
Register
Byte
Write
Register
WEb
OE
Ordering Information
Part Number
IBM041813PQK-4
IBM041813PQK-5
Organization
64K x 18
64K x 18
Speed
4 ns Access / 10 ns Cycle
5 ns Access / 10 ns Cycle
Leads
100 pin TQFP
100 pin TQFP
Notes
50H5206
SA14-4665-01
Revised 3/96
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 14
IBM041813PQK
64K X 18 BURST PIPELINE SRAM
Preliminary
Burst SRAM Clock Truth Table
CLK
CS2
CS2
CS
ADSP
ADSC
ADV
WE
OE
DQ
Operation
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
H
X
H
X
L
L
L
L
X
X
X
X
X
X
X
X
X
X
L
X
L
H
H
H
H
X
X
X
X
X
X
X
X
X
L
L
X
X
L
L
L
L
X
X
X
X
H
H
H
H
H
L
L
X
X
L
L
H
H
H
H
H
H
X
X
X
X
X
X
X
L
L
X
X
L
L
H
H
H
H
L
H
H
H
H
X
X
X
X
X
X
X
X
L
L
H
H
X
L
L
H
H
X
X
X
X
X
X
H
L
H
L
H
L
X
H
L
H
L
X
X
X
X
L
H
L
X
L
X
L
X
X
L
X
L
X
HIZ
HIZ
HIZ
HIZ
Q
HIZ
Q
D
Q
D
Q
D
HIZ
Q
D
Q
D
Deselected Cycle
Deselected Cycle
Deselected Cycle
Deselected Cycle
Read from External
Address, Begin Burst
Read from External
Address, Begin Burst
Read from External
Address, Begin Burst
Write to External
Address, Begin Burst
Read from next Add.,
Continue Burst
Write to next Add.,
Continue Burst
Read from Current
Add., Suspend Burst
Write to Current Add.,
Suspend Burst
Deselect Cycle
Read from next Add.,
Continue Burst
Write to next Add.,
Continue Burst
Read from current
Add., Suspend Burst
Write to current Add.,
Suspend Burst
1. For a write operation preceded by a read cycle, OE must be HIGH early enough to allow Input Data Setup, and must be kept HIGH
through Input Data Hold Time.
2. WE refers to WEa, WEb.
3. ADSP is gated by CS, and CS is used to block ADSP when CS = V
IH
, as required in applications using Processor Address Pipelin-
ing.
4. All Addresses, Data In and Control signals are registered on the rising edge of CLK.
5. Write cycles will put the bus into HIZ on the first rising clock edge according to the Tchz timing. Deselect cycles will put the bus into
HIZ on the second rising edge of clock according to the Tchz timing. If a deselect cycle occurs and WE is enabled within the same
cycle, the part behaves as though it was in a deselect cycle.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H5206
SA14-4665-01
Revised 3/96
Page 4 of 14
Preliminary
IBM041813PQK
64K X 18 BURST PIPELINE SRAM
Burst Sequence Truth Table
(A1,A0)
External Address
1st Access
2nd Access
3rd Access
4th Access
A15-A2
(0,0)
A15-A2
A15-A2
A15-A2
A15-A2
(0,0)
(0,1)
(1,0)
(1,1)
(0,1)
(0,1)
(0,0)
(1,1)
(1,0)
(1,0)
(1,0)
(1,1)
(0,0)
(0,1)
(1,1)
(1,1)
(1,0)
(0,1)
(0,0)
Notes
Write Enable Truth Table
WEa
H
L
L
H
WEb
H
L
H
L
Read All Bytes
Write All Bytes
Write Byte A (D
IN
0 - 8)
Write Byte B (D
IN
9 - 17)
Byte Written
Notes
Absolute Maximum Ratings
Parameter
Power Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
DD
V
IN
V
OUT
T
OPR
T
STG
P
D
I
OUT
Rating
-0.5 to 4.6
-0.5 to 6.0
-0.5 to V
DD
+0.5
0 to +70
-55 to +125
2.0
50
Units
V
V
V
°C
°C
W
mA
Notes
1
1
1
1
1
1
1
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
50H5206
SA14-4665-01
Revised 3/96
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 14
