.
Preliminary
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM
Features
• 512K
×
36 or 1M
×
18 organization
• CMOS technology
• Synchronous pipeline mode of operation with
self-timed late write
• Single differential HSTL clock
• HSTL input and output levels
• +2.5V power supply
• Registered addresses, write enables, synchro-
nous select, and data-ins
• Common I/O
• Asynchronous output enable and sleep mode
inputs
• Boundary scan using a limited set of JTAG
1149.1 functions
• Byte write capability and global write enable
• 7
×
17 bump ball grid array (BGA) package with
SRAM JEDEC standard pinout and boundary
scan order
• Programmable impedance output drivers
Description
The IBM0418166XLAC and IBM0436166XLAC
16Mb SRAM
S
are synchronous pipeline mode, high-
performance CMOS static random-access memo-
ries that have wide I/O and achieve 2-ns cycle times.
Single differential K clocks are used to initiate the
read/write operation, and all internal operations are
self-timed. At the rising edge of the K clock, all
addresses, write enables, synchronous selects, and
data-ins are registered internally. Data-outs are
updated from output registers off the next rising
edge of the K clock. An internal write buffer allows
write data to follow one cycle after addresses and
controls. The chip is operated with a single +2.5V
power supply and is compatible with HSTL I/O inter-
faces.
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November 24, 2003
Page 1 of 25
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM
Preliminary
x36 BGA Bump Layout (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ21
DQ24
V
DDQ
DQ19
DQ25
V
DDQ
DQ28
DQ34
V
DDQ
DQ29
DQ32
NC
NC
V
DDQ
2
SA14
SA18
SA15
DQ20
DQ22
DQ23
DQ18
DQ26
V
DD
DQ27
DQ35
DQ30
DQ31
DQ33
SA16
NC
TMS
3
SA11
SA13
SA12
V
SS
V
SS
V
SS
SBWc
V
SS
V
REF
V
SS
SBWd
V
SS
V
SS
V
SS
M1
1
SA17
TDI
4
NC
NC
V
DD
ZQ
SS
G
NC
NC
V
DD
K
K
SW
SA1
SA0
V
DD
SA2
TCK
5
SA10
SA9
SA8
V
SS
V
SS
V
SS
SBWb
V
SS
V
REF
V
SS
SBWa
V
SS
V
SS
V
SS
M2
1
SA3
TDO
6
SA7
SA6
SA5
DQ15
DQ13
DQ12
DQ17
DQ9
V
DD
DQ8
DQ0
DQ5
DQ4
DQ2
SA4
NC
NC
7
V
DDQ
NC
NC
DQ14
DQ11
V
DDQ
DQ16
DQ10
V
DDQ
DQ7
DQ1
V
DDQ
DQ6
DQ3
NC
ZZ
V
DDQ
1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
SS
and V
DD
, respectively.
x18 BGA Bump Layout (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ10
NC
V
DDQ
NC
DQ12
V
DDQ
NC
DQ17
V
DDQ
DQ15
NC
NC
NC
V
DDQ
2
SA14
SA18
SA15
NC
DQ11
NC
DQ9
NC
V
DD
DQ13
NC
DQ14
NC
DQ16
SA16
SA19
TMS
3
SA11
SA13
SA12
V
SS
V
SS
V
SS
SBWc
V
SS
V
REF
V
SS
NC
V
SS
V
SS
V
SS
M1
1
SA17
TDI
4
NC
NC
V
DD
ZQ
SS
G
NC
NC
V
DD
K
K
SW
SA1
SA0
V
DD
NC
TCK
5
SA10
SA9
SA8
V
SS
V
SS
V
SS
NC
V
SS
V
REF
V
SS
SBWa
V
SS
V
SS
V
SS
M2
1
SA3
TDO
6
SA7
SA6
SA5
DQ7
NC
DQ5
NC
DQ4
V
DD
NC
DQ0
NC
DQ2
NC
SA4
SA2
NC
7
V
DDQ
NC
NC
NC
DQ6
V
DDQ
DQ8
NC
V
DDQ
DQ3
NC
V
DDQ
NC
DQ1
NC
ZZ
V
DDQ
1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
SS
and V
DD
respectively.
Page 2 of 25
XLACds.fm.00
November 24, 2003
Preliminary
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM
Pin Description
SA0–SA19
DQ0–DQ35
K, K
SW
SBWa
SBWb
SBWc
SBWd
Address Input
Data I/O
Differential Input Register Clocks
Write Enable, Global
Write Enable, Byte a (DQ0–DQ8)
Write Enable, Byte b (DQ9–DQ17)
Write Enable, Byte c (DQ18–DQ26)
Write Enable, Byte d (DQ27–DQ35)
G
SS
M1, M2
V
REF
V
DD
V
SS
V
DDQ
ZZ
ZQ
NC
Asynchronous Output Enable
Synchronous Select
Clock Mode Inputs. For this application, M1 and
M2 need to connect to V
SS
and V
DD
, respectively.
HSTL Input Reference Voltage
Power Supply (+2.5V)
Ground
Output Power Supply
Asynchronous Sleep Mode
Output Driver Impedance Control
No Connect
TMS, TDI, TCK IEEE 1149.1 Test Inputs (LVTTL levels)
TDO
IEEE 1149.1 Test Output (LVTTL level)
Ordering Information
Part Number
IBM0418166XLAC-30
IBM0418166XLAC-40
IBM0418166XLAC-50
IBM0436166XLAC-30
IBM0436166XLAC-40
IBM0436166XLAC-50
512K
×
36
1M
×
18
Organization
Speed (Cycle Time) (ns)
3.0
4.0
5.0
3.0
4.0
5.0
7
×
17 BGA
Leads
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November 24, 2003
Page 3 of 25
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM
Preliminary
Block Diagram
Row Decoder
SA0–SA19
K
SS
ZZ
SW
SBW
Latch
SW
Register
SBW
Register
SW
Register
SBW
Register
Latch
RD Add
Register
WR Add
Register
2:1 MUX
512K
×
36
or
1M
×
18
Array
Column Decoder
Read/Write Amp
Match
2:1 MUX
Write
Buffer
SS
Register
SS
Register
Data Out
Register
G
DQ0–DQ35 or DQ0–DQ17
SRAM Features
Late Write
The late-write function allows write data to be registered one cycle after addresses and controls. This feature
eliminates one of two bus-turnaround cycles normally required when going from a read to a write operation.
Late write is accomplished by buffering write addresses and data. The SRAM array update occurs during the
third write cycle. Read-cycle addresses are monitored to determine if the SRAM array or the write buffer will
supply read data.
During a write, the byte writes control which byte of data will be written for a given address (see the
Clock
Truth Table
on page 6).
Page 4 of 25
XLACds.fm.00
November 24, 2003
Preliminary
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM
Mode Control
Mode control pins M1 and M2 are used to select four different read protocols:
• Single clock, flow-through (M1 = V
SS
, M2 = V
SS
)
• Pipeline (M1 = V
SS
, M2 = V
DD
)
• Register-latch (M1 = V
DD
, M2 = V
SS
)
• Dual clock, flow-through (M1 = V
DD
, M2 = V
DD
)
This datasheet only describes pipeline functionality. Mode control inputs must be set at power-up, and must
not change during SRAM operation.
Sleep Mode
Sleep mode is enabled by switching the asynchronous signal, ZZ, to high. When the SRAM is in sleep mode,
the outputs go to a High-Z state, and the SRAM draws standby current. SRAM data is preserved, and a
recovery time (t
ZZR
) is required before the SRAM resumes normal operation.
Programmable Impedance/Power Up Requirements
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V
SS
to allow the SRAM to
adjust its output driver impedance. The value of RQ must be five times the value of the intended line imped-
ance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of
15% is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary because
the impedance is affected by drifts in supply voltage and temperature. One evaluation occurs every 64 clock
cycles, and each evaluation may move the output driver impedance level, one step at a time, towards the
optimum level. The output driver has 64 discrete binary weighted steps. Impedance updates for zeros occur
whenever the SRAM is driving ones for the same DQs; impedance updates for ones occur whenever SRAM
is driving zeros for the same DQs. Updates of both zeros and ones occur when the SRAM is in a High-Z
state. The SRAM requires 4µs of power-up time after V
DD
reaches its operating range. Furthermore, to guar-
antee the output driver impedance, the SRAM requires 2048 clock cycles and a Read '0' and Read '1' or a
Read '1' and a Read '0' across all outputs. The RC time constant of the loaded RQ trace must be less than
3ns.
Power-Up/Power-Down Sequence
The power supplies need to be powered up in the following sequence: V
DD
, V
DDQ
, V
REF
, followed by inputs.
The power down sequence must be the reverse. V
DDQ
must not exceed V
DD
.
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November 24, 2003
Page 5 of 25
实时操作系统RTOS
