IBM0436A41NLAB IBM0418A41NLAB
IBM0418A81NLAB IBM0436A81NLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
.
Features
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• 0.25 Micron CMOS technology
• Common I/O
• Synchronous pipeline mode of operation with
self-timed late write
• Differential PECL clocks or 2.5V LVTTL swing
with one clock tied to V
DDQ
/2
• +3.3V power supply, ground, 2.5V V
DDQ
• 2.5V LVTTL input and output levels
• Registered addresses, write enables, synchro-
nous select, and data ins
• Asynchronous output enable
• Synchronous power down input
• Boundary scan using limited set of JTAG 1149.1
functions
• Byte write capability and global write enable
• 7 x 17 bump ball grid array package with SRAM
JEDEC standard pinout and boundary SCAN
order
• Registered outputs
• 30
Ω
drivers
Description
The 4Mb and 8Mb SRAMs—IBM0436A41NLAB,
IBM0418A41NLAB, IBM0418A81NLAB, and
IBM0436A81NLAB—are synchronous pipeline
mode, high-performance CMOS static random-
access memories that are versatile, have wide I/O,
and can achieve 3.0ns cycle times. Differential K
clocks are used to initiate the read/write operation
and all internal operations are self-timed. At the ris-
ing edge of the K clock, all addresses, write-
enables, synchronous select, and data ins are regis-
tered internally. Data outs are updated from output
registers on the next rising edge of the K clock. An
internal write buffer allows write data to follow one
cycle after addresses and controls. The device is
operated with a single +3.3V power supply and is
compatible with a 2.5V LVTTL I/O interface.
crrL3325.06.fm
June 13, 2002
Page 1 of 25
IBM0436A41NLAB IBM0418A41NLAB
IBM0418A81NLAB IBM0436A81NLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
x36 BGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ19
DQ22
V
DDQ
DQ24
DQ25
V
DDQ
DQ34
DQ33
V
DDQ
DQ31
DQ28
NC
NC
V
DDQ
2
SA
NC
SA
DQ18
DQ20
DQ21
DQ23
DQ26
V
DD
DQ35
DQ32
DQ30
DQ29
DQ27
SA
NC
TMS
3
SA
SA
SA
V
SS
V
SS
V
SS
SBWc
V
SS
NC
V
SS
SBWd
V
SS
V
SS
V
SS
M1
1
SA
TDI
4
NC
NC
V
DD
NC
SS
G
NC
NC
V
DD
K
K
SW
SA
SA
V
DD
SA
TCK
5
SA
SA
SA
V
SS
V
SS
V
SS
SBWb
V
SS
NC
V
SS
SBWa
V
SS
V
SS
V
SS
M2
1
SA
TDO
6
SA
NC, SA (8Mb)
SA
DQ9
DQ11
DQ12
DQ14
DQ17
V
DD
DQ8
DQ5
DQ3
DQ2
DQ0
SA
NC
NC
7
V
DDQ
NC
NC
DQ10
DQb13
V
DDQ
DQb15
DQb16
V
DDQ
DQ7
DQ6
V
DDQ
DQ4
DQ1
NC
ZZ
V
DDQ
1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
SS
and V
DD
, respectively.
x18 BGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ14
NC
V
DDQ
NC
DQ17
V
DDQ
NC
DQ12
V
DDQ
DQ11
NC
NC
NC
V
DDQ
2
SA
NC
SA
NC
DQ15
NC
DQ16
NC
V
DD
DQ13
NC
DQ10
NC
DQ9
SA
SA
TMS
3
SA
SA
SA
V
SS
V
SS
V
SS
SBWb
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
M1
1
SA
TDI
4
NC
NC
V
DD
NC
SS
G
NC
NC
V
DD
K
K
SW
SA
SA
V
DD
NC
TCK
5
SA
SA
SA
V
SS
V
SS
V
SS
NC
V
SS
NC
V
SS
SBWa
V
SS
V
SS
V
SS
M2
1
SA
TDO
6
SA
NC, SA (8Mb)
SA
DQ0
NC
DQ2
NC
DQ4
V
DD
NC
DQ7
NC
DQ6
NC
SA
SA
NC
7
V
DDQ
NC
NC
NC
DQ1
V
DDQ
DQ3
NC
V
DDQ
DQ8
NC
V
DDQ
NC
DQ5
NC
ZZ
V
DDQ
1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
SS
and V
DD
, respectively.
Page 2 of 25
crrL3325.06.fm
June 13, 2002
IBM0436A41NLAB IBM0418A41NLAB
IBM0418A81NLAB IBM0436A81NLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
Address Input
SA0-SA18 for 512K x 18
SA0-SA17 for 256K x 36
SA0-SA17 for 256K x 18
SA0-SA16 for 128K x 36
Data I/O
DQ0-DQ17 for 512K x 18
DQ0-DQ35 for 256K x 36
Differential Input Register Clocks
Write Enable, Global
Write Enable, Byte a (DQ0-DQ8)
Write Enable, Byte b (DQ9-DQ17)
Write Enable, Byte c (DQ18-DQ26)
Write Enable, Byte d (DQ27-DQ35)
IEEE
®
1149.1 Test Inputs (LVTTL levels)
IEEE 1149.1 Test Output (LVTTL level)
SA0-SA18
G
Asynchronous Output Enable
DQ0-DQ35
SS
Synchronous Select
K, K
SW
SBWa
SBWb
SBWc
SBWd
TMS, TDI, TCK
TDO
M1, M2
V
DD
V
SS
V
DDQ
ZZ
NC
Clock Mode Inputs - Selects Single or Dual
Clock Operation.
Power Supply (+3.3V)
Ground
Output Power Supply
Synchronous Sleep Mode
No Connect
crrL3325.06.fm
June 13, 2002
Page 3 of 25
IBM0436A41NLAB IBM0418A41NLAB
IBM0418A81NLAB IBM0436A81NLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Ordering Information
Part Number
IBM0418A41NLAB - 3
IBM0418A41NLAB - 3F
IBM0418A41NLAB - 3N
IBM0418A41NLAB - 4
IBM0418A41NLAB - 5
IBM0436A41NLAB - 3
IBM0436A41NLAB - 3F
IBM0436A41NLAB - 3N
IBM0436A41NLAB - 4
IBM0436A41NLAB - 5
IBM0418A81NLAB - 3
IBM0418A81NLAB - 3F
IBM0418A81NLAB - 3N
IBM0418A81NLAB - 4
IBM0418A81NLAB - 5
IBM0436A81NLAB - 3
IBM0436A81NLAB - 3F
IBM0436A81NLAB - 3N
IBM0436A81NLAB - 4
IBM0436A81NLAB - 5
Organization
256K x 18
256K x 18
256K x 18
256K x 18
256K x 18
128K x 36
128K x 36
128K x 36
128K x 36
128K x 36
512K x 18
512K x 18
512K x 18
512K x 18
512K x 18
256K x 36
256K x 36
256K x 36
256K x 36
256K x 36
Speed
1.8ns Access / 3.0ns Cycle
2.0ns Access / 3.3ns Cycle
2.0ns Access / 3.7ns Cycle
2.25ns Access / 4.0ns Cycle
2.5ns Access / 5.0ns Cycle
1.8ns Access / 3.0ns Cycle
2.0ns Access / 3.3ns Cycle
2.0ns Access / 3.7ns Cycle
2.25ns Access / 4.0ns Cycle
2.5ns Access / 5.0ns Cycle
1.8ns Access / 3.0ns Cycle
2.0ns Access / 3.3ns Cycle
2.0ns Access / 3.7ns Cycle
2.25ns Access / 4.0ns Cycle
2.5ns Access / 5.0ns Cycle
1.8ns Access / 3.0ns Cycle
2.0ns Access / 3.3ns Cycle
2.0ns Access / 3.7ns Cycle
2.25ns Access / 4.0ns Cycle
2.5ns Access / 5.0ns Cycle
Leads
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
Page 4 of 25
crrL3325.06.fm
June 13, 2002
IBM0436A41NLAB IBM0418A41NLAB
IBM0418A81NLAB IBM0436A81NLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Block Diagram
SBW
REG
SBW
READ
ADD REG
WRITE0
ADD REG
WRITE1
ADD REG
SBW0
REG
Row Decode
SA0-SA18
DOC_MUX0
2:1 MUX
DOC_Array0
READ
K
Col Decode
Read/Wr Amp
WRITE
LATCH
MATCH1
MATCH
SS
WR_BUF1
ZZ
SW
LATCH0
DOC_MUX2
2:1 MUX
SW0
REG
SW1
REG
DOC_MUX1
2:1 MUX
SS0
REG
SS1
REG
DOC_
DOUT0
G
DQ0-DQ35
crrL3325.06.fm
June 13, 2002
Page 5 of 25
WR_BUF0
