.
Preliminary
Features
IBM0418A4ANLAB IBM0418A8ANLAB
IBM0436A8ANLAB IBM0436A4ANLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
• 8Mb: 256K x 36 or 512K x 18 organizations
4Mb: 128K x 36 or 256K x 18 organizations
• 0.25µ CMOS technology
• Synchronous Register-Latch Mode of Operation
with Self-Timed Late Write
• Single Differential PECL Clock
• +3.3V Power Supply, Ground, 2.5V V
DDQ
• 2.5V LVTTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
• Latched Outputs
• Common I/O
• 30Ω Drivers
• Asynchronous Output Enable and Power Down
Inputs
• Boundary Scan using limited set of JTAG
1149.1 functions
• Byte Write Capability & Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
Description
IBM0436A4ANLAB, IBM0436A8ANLAB,
IBM0418A4ANLAB, and IBM0418A8ANLAB are
4Mb and 8Mb Synchronous Register-Latch Mode,
high-performance CMOS Static Random Access
Memories (SRAMs). These SRAMs are versatile,
have a wide input/output (I/O) interface, and can
achieve cycle times as short as 4.5ns. Differential K
clocks are used to initiate the read/write operation;
all internal operations are self-timed. At the rising
edge of the K clock, all address, write-enables, sync
select, and data input signals are registered inter-
nally. Data outputs are updated from output regis-
ters off the falling edge of the K clock. An internal
write buffer allows write data to follow one cycle
after addresses and controls. The device is oper-
ated with a single +3.3V power supply and is com-
patible with 2.5V LVTTL I/O interfaces.
crlL3325.03
08/06/2001
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 24
IBM0418A4ANLAB IBM0418A8ANLAB
IBM0436A8ANLAB IBM0436A4ANLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
x36 BGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ19
DQ22
V
DDQ
DQ24
DQ25
V
DDQ
DQ34
DQ33
V
DDQ
DQ31
DQ28
NC
NC
V
DDQ
2
SA
NC
SA
DQ18
DQ20
DQ21
DQ23
DQ26
V
DD
DQ35
DQ32
DQ30
DQ29
DQ27
SA
NC
TMS
3
SA
SA
SA
V
SS
V
SS
V
SS
SBWc
V
SS
NC
V
SS
SBWd
V
SS
V
SS
V
SS
M1*
SA
TDI
4
NC
NC
V
DD
NC
SS
G
NC
NC
V
DD
K
K
SW
SA
SA
V
DD
SA
TCK
5
SA
SA
SA
V
SS
V
SS
V
SS
SBWb
V
SS
NC
V
SS
SBWa
V
SS
V
SS
V
SS
M2*
SA
TDO
6
SA
NC,SA(8Mb)
SA
DQ9
DQ11
DQ12
DQ14
DQ17
V
DD
DQ8
DQ5
DQ3
DQ2
DQ0
SA
NC
NC
7
V
DDQ
NC
NC
DQ10
DQb13
V
DDQ
DQb15
DQb16
V
DDQ
DQ7
DQ6
V
DDQ
DQ4
DQ1
NC
ZZ
V
DDQ
* M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
DD
and V
SS
respectively.
x18 BGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ14
NC
V
DDQ
NC
DQ17
V
DDQ
NC
DQ12
V
DDQ
DQ11
NC
NC
NC
V
DDQ
2
SA
NC
SA
NC
DQ15
NC
DQ16
NC
V
DD
DQ13
NC
DQ10
NC
DQ9
SA
SA
TMS
3
SA
SA
SA
V
SS
V
SS
V
SS
SBWb
V
SS
NC
V
SS
NC
V
SS
V
SS
V
SS
M1
SA
TDI
4
NC
NC
V
DD
NC
SS
G
NC
NC
V
DD
K
K
SW
SA
SA
V
DD
NC
TCK
5
SA
SA
SA
V
SS
V
SS
V
SS
NC
V
SS
NC
V
SS
SBWa
V
SS
V
SS
V
SS
M2
SA
TDO
6
SA
NC,SA(8Mb)
SA
DQ0
NC
DQ2
NC
DQ4
V
DD
NC
DQ7
NC
DQ6
NC
SA
SA
NC
7
V
DDQ
NC
NC
NC
DQ1
V
DDQ
DQ3
NC
V
DDQ
DQ8
NC
V
DDQ
NC
DQ5
NC
ZZ
V
DDQ
* M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to V
DD
and V
SS
respectively.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
crlL3325.03
08/06/2001
Page 2 of 24
Preliminary
IBM0418A4ANLAB IBM0418A8ANLAB
IBM0436A8ANLAB IBM0436A4ANLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
Address Input
SA0-SA18 for 512K x 18
SA0-SA17 for 256K x 36
SA0-SA17 for 256K x 18
SA0-SA16 for 128K x 36
Data I/O
DQ0-DQ17 for 512K x 18
DQ0-DQ35 for 256K x 36
Differential Input Register Clocks
Write Enable, Global
Write Enable, Byte a (DQ0-DQ8)
Write Enable, Byte b (DQ9-DQ17)
Write Enable, Byte c (DQ18-DQ26)
Write Enable, Byte d (DQ27-DQ35)
IEEE
®
1149.1 Test Inputs (LVTTL levels)
SA0-SA18
TDO
IEEE 1149.1 Test Output (LVTTL level)
DQ0-DQ35
G
Asynchronous Output Enable
K, K
SW
SBWa
SBWb
SBWc
SBWd
TMS, TDI, TCK
SS
M1, M2
V
DD
V
SS
V
DDQ
ZZ
NC
Synchronous Select
Clock Mode Inputs. Selects Single or Dual Clock
Operation.
Power Supply (+3.3V)
Ground
Output Power Supply
Synchronous Sleep Mode
No Connect
Ordering Information
Part Number
IBM0436A8ANLAB - 4H
IBM0436A8ANLAB - 5
IBM0436A8ANLAB - 5H
IBM0436A4ANLAB - 4H
IBM0436A4ANLAB - 5
IBM0436A4ANLAB - 5H
IBM0418A4ANLAB - 4H
IBM0418A4ANLAB - 5
IBM0418A4ANLAB - 5H
IBM0418A8ANLAB -4H
IBM0418A8ANLAB -5
IBM0418A8ANLAB -5H
Organization
256K x 36
256K x 36
256K x 36
128K x 36
128K x 36
128K x 36
256K x 18
256K x 18
256K x 18
512K x 18
512K x 18
512K x 18
Speed
4.5ns Access / 4.5ns Cycle
5.0ns Access / 5.0ns Cycle
5.5ns Access / 5.5ns Cycle
4.5ns Access / 4.5ns Cycle
5.0ns Access / 5.0ns Cycle
5.5ns Access / 5.5ns Cycle
4.5ns Access / 4.5ns Cycle
5.0ns Access / 5.0ns Cycle
5.5ns Access / 5.5ns Cycle
4.5ns Access / 4.5ns Cycle
5.0ns Access / 5.0ns Cycle
5.5ns Access / 5.5ns Cycle
Leads
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
7 x 17 BGA
crlL3325.03
08/06/2001
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 24
IBM0418A4ANLAB IBM0418A8ANLAB
IBM0436A8ANLAB IBM0436A4ANLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
Block Diagram
SBW
REG
SBW
READ
ADD REG
WRITE0
ADD REG
WRITE1
ADD REG
SBW0
REG
Row Decode
SA0-SA18
DOC_MUX0
2:1 MUX
DOC_Array0
READ
K
Col Decode
Read/Wr Amp
LATCH
MATCH1
MATCH
SS
ZZ
WRITE
WR_BUF1
SW
LATCH0
DOC_MUX2
2:1 MUX
SW0
REG
SW1
REG
DOC_MUX1
2:1 MUX
DOC_
DOUT0
G
DQ0-DQ35
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 24
WR_BUF0
crlL3325.03
08/06/2001
Preliminary
IBM0418A4ANLAB IBM0418A8ANLAB
IBM0436A8ANLAB IBM0436A4ANLAB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
SRAM Features
Late Write
The Late Write function allows for write data to be registered one cycle after addresses and controls. This fea-
ture eliminates one bus-turnaround cycle, necessary when going from a read to a write operation. Late write
is accomplished by buffering write addresses and data so that the write operation occurs during the next write
cycle. When a read cycle occurs after a write cycle, the address and write data information are stored tempo-
rarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array is updated
with address and data from the holding registers. Read cycle addresses are monitored to determine if read
data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array occurs on a
byte-by-byte basis. When only one byte is written during a write cycle, read data from the last written address
has new byte data from the write buffer and remaining bytes from the SRAM array.
Mode Control
Mode control pins M1 and M2 are used to select four different JEDEC-standard read protocols. This SRAM
supports single clock, register latch operation (M1 = V
DD
, M2 = V
SS
). This datasheet describes single clock
register latch functionality only. Mode control inputs must be set at power up and must not change during
SRAM operation. This SRAM is tested only in the register-latch mode.
Sleep Mode
The sleep mode is enabled by switching the synchronous signal ZZ High. When the SRAM is in the sleep
mode, the outputs go to a High-Z state and the SRAM draws standby current. SRAM data is preserved and a
recovery time (t
ZZR
) is required before the SRAM resumes normal operation.
Power-Up Requirements
To ensure the optimum internally regulated supply voltage, the SRAM requires 4µs of power-up time after
V
DD
reaches its operating range.
Power-Up and Power-Down Sequencing
The power supplies must be powered up in the following order: V
DD
, V
DDQ
, and Inputs. The power-down
sequence must be in the reverse order. V
DDQ
may not exceed V
DD
by more than 0.6V. No special tracking
between power supplies is required.
crlL3325.03
08/06/2001
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 24
