.
Advance
Features
IBM0418A8CXLBB IBM0436A8CXLBB
IBM0418A4CXLBB IBM0436A4CXLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
• 8Mb: 256K x 36 or 512K x 18 Organizations
• 4Mb: 128K x 36 or 256K x 18 Organizations
• CMOS Technology
• Double Data Rate and Single Data Rate Syn-
chronous Modes of Operation
• Pipeline Mode of Operation
• Self-Timed Late Write with Full Data Coherency
• Single Differential HSTL Clock
• +2.5V Power Supply, Ground, 1.6V V
DDQ
, and
0.95V V
REF
• HSTL Input and Output levels
• Registered Addresses, Controls, and Data Ins.
• Burst Mode of operation
• Common I/O
• Asynchronous Output Enable
• Boundary Scan using limited set of JTAG
1149.1 functions
• 9 x 17 Bump Ball Grid Array Package with
SRAM JEDEC Standard Pinout and Boundary
SCAN Order
• Programmable Impedance Output Drivers
Description
The IBM0436A4CXLBB, IBM0418A4CXLBB,
IBM0418A8CXLBB, and IBM0436A8CXLBB
SRAM
S
are Synchronous Pipeline Mode, high-per-
formance CMOS Static Random Access Memories
that are versatile, have wide I/O, and achieve 4ns
cycle times. Differential CK clocks are used to ini-
tiate the read/write operation and all internal opera-
tions are self-timed. At the rising edge of the CK
clock, all Addresses, Controls, and Data Ins are reg-
istered internally. Data Outs are updated from out-
put registers off the next rising and falling edge of
the K clock, hence the Double Data Rate. Internal
Write buffers allow write data to follow one cycle
after addresses and controls. The chip is operated
with a single +2.5V power supply and is compatible
with HSTL I/O interfaces.
tddrh2516.01
8/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 5
IBM0418A8CXLBB IBM0436A8CXLBB
IBM0418A4CXLBB IBM0436A4CXLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
x36 BGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
2
VDDQ
DQ
VDDQ
DQ
VDDQ
CQ
VDDQ
DQ
VDDQ
DQ
VDDQ
CQ
VDDQ
DQ
VDDQ
DQ
VDDQ
3
SA
SA
SA
NC
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
NC
VDD
SA
TMS
4
SA
VSS
SA
VSS
VDD
VDD
VSS
VDD
VDD
VSS
LBO
VDD
VDD
VSS
SA
VSS
TDI
5
ZQ
B1(LD)
G
VDD
VREF
VDD
CK
CK
VDD
B2(WE)
B3(DDR)
VDD
VREF
VDD
SA1
SA0
TCK
6
SA
VSS
SA
VSS
VDD
VDD
VSS
VDD
VDD
VSS
NC
VDD
VDD
VSS
SA
VSS
TDO
7
SA
SA
SA
SA(8M)
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
SA
VDD
SA
NC
8
VDDQ
DQ
VDDQ
DQ
VDDQ
CQ
VDDQ
DQ
VDDQ
DQ
VDDQ
CQ
VDDQ
DQ
VDDQ
DQ
VDDQ
9
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
DQ
VSS
x18 BGA Pinout
(Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
2
VDDQ
DQ
VDDQ
NC
VDDQ
CQ
VDDQ
NC
VDDQ
DQ
VDDQ
NC
VDDQ
DQ
VDDQ
NC
VDDQ
3
SA
SA
SA
NC
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
SA
VDD
SA
TMS
4
SA
VSS
SA
VSS
VDD
VDD
VSS
VDD
VDD
VSS
LBO
VDD
VDD
VSS
SA
VSS
TDI
5
ZQ
B1(LD)
G
VDD
VREF
VDD
CK
CK
VDD
B2(WE)
B3(DDR)
VDD
VREF
VDD
SA1
SA0
TCK
6
SA
VSS
SA
VSS
VDD
VDD
VSS
VDD
VDD
VSS
NC
VDD
VDD
VSS
SA
VSS
TDO
7
SA
SA
SA
SA(8M)
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
SA
VDD
SA
NC
8
VDDQ
NC
VDDQ
DQ
VDDQ
NC
VDDQ
DQ
VDDQ
NC
VDDQ
CQ
VDDQ
NC
VDDQ
DQ
VDDQ
9
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
DQ
VSS
NC
VSS
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
tddrh2516.01
8/99
Page 2 of 5
Preliminary
IBM0418A8CXLBB IBM0436A8CXLBB
IBM0418A4CXLBB IBM0436A4CXLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
Address Inputs
SA0-SA1 Burst control starting addresses
SA0-SA18 for 512Kx18
SA0-SA17 for 256Kx36
SA0-SA17 for 256Kx18
SA0-SA16 for 128Kx36
Data I/O
DQ0-DQ17 for 512Kx18
DQ0-DQ35 for 256Kx36
Output Differential Echo Clocks
Differential Input Register Clocks
Synchronous Function Control Input. B1 = 0
Loads a new Address
Synchronous Function Control Input (WE). B2
= 0 starts Write & B2 = 1 starts Read.
Synchronous Function Control Input. B3 = 0
starts a DDR (Burst) operation. B3 = 1 starts a
SDR (Single Data Rate)
Linear Burst Order, (LBO =1 interleave mode,
LBO = 0 linear mode)
Asynchronous Output Enable
SA0-SA18
TMS,TDI,TCK IEEE 1149.1 Test Inputs (LVTTL levels)
DQ0-DQ35
TDO
IEEE 1149.1 Test Output (LVTTL level)
CQ, CQ
CK, CK
B1
V
REF
(2)
V
DD
V
SS
V
DDQ
HSTL Input Reference Voltage
Power Supply (+2.5V)
Ground
B2
Output Power Supply
B3
ZQ
Input pin for Output Driver Impedance Control.
LBO
G
NC
No Connect
Ordering Information
Part Number
IBM0418A4CXLBB-3
IBM0418A4CXLBB-4
IBM0418A4CXLBB-5
IBM0436A4CXLBB-3
IBM0436A4CXLBB-4
IBM0436A4CXLBB-5
IBM0418A8CXLBB-3
IBM0418A8CXLBB-4
IBM0418A8CXLBB-5
IBM0436A8CXLBB-3
IBM0436A8CXLBB-4
IBM0436A8CXLBB-5
256K x 36
512K x 18
256K x 36
512K x 18
Organization
Speed
2.0ns Access / 3.5ns Cycle
2.0ns Access / 4.0ns Cycle
2.5ns Access / 5.0ns Cycle
2.0ns Access / 3.5ns Cycle
2.0ns Access / 4.0ns Cycle
2.5ns Access / 5.0ns Cycle
9 x 17 BGA
2.0ns Access / 3.5ns Cycle
2.0ns Access / 4.0ns Cycle
2.5ns Access / 5.0ns Cycle
2.0ns Access / 3.5ns Cycle
2.0ns Access / 4.0ns Cycle
2.5ns Access / 5.0ns Cycle
Leads
tddrh2516.01
8/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 5
IBM0418A8CXLBB IBM0436A8CXLBB
IBM0418A4CXLBB IBM0436A4CXLBB
8Mb (256Kx36 & 512Kx18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
Revision Log
Date
8/99
Initial release.
Contents of Modification
For a complete datasheet, please contact your IBM sales representative.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
tddrh2516.01
8/99
Page 4 of 5
®
©
Intern
ational Business Machines Corp.1999
Copyright
Printed in the United States of America
All rights reserved
IBM and the IBM logo are registered trademarks of the IBM Corporation.
This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or
liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or
indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for
use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons.
NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
For more information contact your IBM Microelectronics sales representative or
visit us on World Wide Web at http://www.chips.ibm.com
IBM Microelectronics manufacturing is ISO 9000 compliant.
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