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IBM PowerPC 750GL RISC Microprocessor

Revision Level DD1.X

Datasheet

Version: 1.2

Preliminary

March 13, 2006

Printed in the United States of America March 2006.

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PowerPC 750

PowerPC Architecture

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750GL_ds_title.fm 1.2

March 13, 2006

Preliminary

Datasheet

DD 1.X

PowerPC 750GL RISC Microprocessor

1. General Information .................................................................................................... 9

1.1 Features ............................................................................................................................................ 9

1.3 Processor Version Register ............................................................................................................ 11

1.4 Part Number Information ................................................................................................................. 12

2. Overview .................................................................................................................... 13

2.1 Block Diagram ................................................................................................................................. 13

2.2 General Parameters ........................................................................................................................ 14

3. Electrical and Thermal Characteristics ................................................................... 15

3.1 DC Electrical Characteristics ...........................................................................................................

3.2 AC Electrical Characteristics ...........................................................................................................

3.3 Clock AC Specifications ..................................................................................................................

3.4 Spread Spectrum Clock Generator .................................................................................................

3.4.1 Design Considerations ..........................................................................................................

3.5.1 Input Setup Timing ................................................................................................................

3.6 60x Bus Output AC Specifications ..................................................................................................

3.6.1 IEEE 1149.1 AC Timing Specifications .................................................................................

4. Dimensions and Signal Assignments ..................................................................... 30

4.1 Package .......................................................................................................................................... 30

4.2 Module Substrate Decoupling Voltage Assignments ...................................................................... 35

4.3 Microprocessor Ball Placement ....................................................................................................... 36

5. System Design Information ..................................................................................... 46

5.1 PLL Operation .................................................................................................................................

5.1.1 Overview ................................................................................................................................

5.1.2 Restrictions and Considerations for PLL Configuration .........................................................

5.1.2.1 Configuration Restriction on Frequency Transitions ......................................................

5.1.3 PLL_RNG[0:1] Definitions for Dual PLL Operation ................................................................

5.1.4 PLL Configuration ..................................................................................................................

5.2 PLL Power Supply Filtering .............................................................................................................

5.3 Decoupling Recommendations .......................................................................................................

5.4 Connection Recommendations .......................................................................................................

5.5 Output Buffer DC Impedance ..........................................................................................................

5.5.1 Input/Output Usage ...............................................................................................................

5.6 Thermal Management Information ..................................................................................................

5.6.1 Thermal Assist Unit ...............................................................................................................

5.6.2 Minimum Heat Sink Requirements ........................................................................................

5.6.3 Internal Package Conduction Resistance ..............................................................................

5.6.4 Adhesives and Thermal Interface Materials ..........................................................................

5.7 Heat-Sink Selection Example ..........................................................................................................

5.8 Operational and Design Considerations .........................................................................................

5.8.1 Level Protection .....................................................................................................................

5.8.2 64-Bit or 32-Bit Data Bus Mode .............................................................................................

5.8.4 QACK Signal Implementation for Selected Features ............................................................

5.8.4.1 Precharge Duration Selection and Application ...............................................................

750GL_dsTOC.fm.1.2

March 13, 2006

Page 3 of 74

Datasheet

DD 1.X

PowerPC 750GL RISC Microprocessor

Preliminary

5.8.4.2 Processor Debug System Enablement when Implementing Precharge Selection ......... 72

Revision Log ................................................................................................................. 73

Page 4 of 74

750GL_dsTOC.fm.1.2

March 13, 2006

Preliminary

Datasheet

DD 1.X

PowerPC 750GL RISC Microprocessor

Table 1-1.

Table 2-1.

Table 3-1.

Table 3-2.

Table 3-3.

Table 3-4.

Table 3-5.

Table 3-6.

Table 3-7.

Table 3-8.

Table 3-9.

Table 3-10.

Table 4-1.

Table 4-2.

Table 4-3.

Table 4-4.

Table 5-1.

Table 5-2.

Table 5-3.

Table 5-4.

Table 5-5.

Table 5-6.

Table 5-7.

Table 5-8.

Table 5-9.

Table 5-10.

750GL Processor Version Register (PVR) ............................................................................. 11

750GL General Parameters ................................................................................................... 14

Absolute Maximum Ratings ................................................................................................... 15

Recommended Operating Conditions .................................................................................... 15

Package Thermal Characteristics .......................................................................................... 16

DC Electrical Specifications ................................................................................................... 16

Power Consumption (Low Power) .......................................................................................... 17

Power Consumption (Standard Power) .................................................................................. 17

Clock AC Timing Specifications ............................................................................................. 19

60x Bus Input AC Timing Specifications ................................................................................ 21

60x Bus Output AC Timing Specifications ............................................................................. 24

JTAG AC Timing Specifications (Independent of SYSCLK) .................................................. 27

Pinout Listing for the CBGA package ..................................................................................... 37

Signal Listing for the CBGA Package .................................................................................... 40

Signal Locations ..................................................................................................................... 43

Voltage and Ground Assignments ......................................................................................... 45

PLL_RNG[0:1] Definitions for Dual PLL Operation ................................................................ 47

750GL Microprocessor PLL Configuration ............................................................................. 48

Sample PLL Power Supply Filtering Circuits .......................................................................... 50

Recommended Decoupling Capacitor Specifications ............................................................ 54

Driver Impedance Characteristics .......................................................................................... 58

Input/Output Usage ................................................................................................................ 59

Maximum Heat-Sink Weight Limit for the CBGA .................................................................... 63

750GL Heat-Sink Vendors ..................................................................................................... 64

750GL Thermal Interface and Adhesive Materials Vendors .................................................. 68

Summary of Mode Select ....................................................................................................... 71

750GL_dsLOT.fm.1.2

March 13, 2006

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