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IBM PowerPC

970FX RISC Microprocessor

Data Sheet

Preliminary Electrical Information

SA14-2760-05

Version 2.1

Preliminary

October 14, 2005

Printed in the United States of America October 2005

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PowerPC

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PowerPC 970

PowerPC Architecture

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Note:

All information contained in this document is subject to change without notice. Verify with your IBM field

application enginner that you have the latest version of this document before finalizing a design.

The products described in this document are NOT intended for use in applications such as implantation, life

support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic prop-

erty damage. Nothing in this document shall operate as an express or implied license or indemnity under the

intellectual property rights of IBM or third parties, or give rise to any express or implied warranty. Information

contained in this document was obtained in specific environments, and is presented as an illustration. The

results obtained in other operating environments may vary.

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liable for damages arising directly or indirectly from any use of the information contained in this document.

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October 14, 2005

Preliminary

Data Sheet

PowerPC 970FX

About This Datasheet .................................................................................................... 9

1. General Information .................................................................................................. 11

1.1 Description ....................................................................................................................................

1.2 Features .........................................................................................................................................

1.3 PowerPC 970FX Block Diagram ...................................................................................................

1.4 Ordering and Processor Version Register .................................................................................

1.4.1 Leaded Package Version ......................................................................................................

1.4.2 Reduced-Lead Package Version ...........................................................................................

2. General Parameters .................................................................................................. 17

3. Electrical and Thermal Characteristics ................................................................... 17

3.1 DC Electrical Characteristics .......................................................................................................

3.1.1 Absolute Maximum Ratings ...................................................................................................

3.1.2 Recommended Operating Conditions ...................................................................................

3.1.3 Package Thermal Characteristics ..........................................................................................

3.1.4 DC Electrical Specifications ...................................................................................................

3.1.5 Power Consumption ..............................................................................................................

3.2 AC Electrical Characteristics .......................................................................................................

3.3 Clock AC Specifications ...............................................................................................................

3.4 Processor-Clock Timing Relationship Between PSYNC and SYSCLK ....................................

3.5 Processor Interconnect Specifications .......................................................................................

3.5.1 Electrical and Physical Specifications ...................................................................................

3.5.1.1 Source Synchronous Bus (SSB) ....................................................................................

3.5.1.2 Drive Side Characteristics ..............................................................................................

3.5.1.3 Module-to-Module Interconnect Characteristics .............................................................

3.5.1.4 Receive Side Characteristics .........................................................................................

3.6 Input AC Specifications ................................................................................................................

3.6.1 TBEN Input Pin ......................................................................................................................

3.7 Asynchronous Output Specifications .........................................................................................

3.8 Mode Select Input Timing Specifications ...................................................................................

3.9 Spread Spectrum Clock Generator (SSCG) ................................................................................

3.9.1 Design Considerations ..........................................................................................................

3.10 I

C and JTAG ...............................................................................................................................

3.10.1 I

C Bus Timing Information .................................................................................................

3.10.2 IEEE 1149.1 AC Timing Specifications ...............................................................................

3.10.3 I2C and JTAG Considerations .............................................................................................

3.10.4 Boundary Scan Considerations ...........................................................................................

4. PowerPC 970FX Microprocessor Dimension and Physical Signal Assignments 40

4.1 ESD Considerations ......................................................................................................................

4.2 Mechanical Packaging ..................................................................................................................

4.2.1 Leaded Package Version ......................................................................................................

4.2.2 Reduced-Lead Package Version ...........................................................................................

4.2.2.1 Mechanical Specifications ..............................................................................................

4.2.2.2 Assembly Considerations ...............................................................................................

October 14, 2005

Page 3 of 74

Data Sheet

PowerPC 970FX

Preliminary

4.3 PowerPC 970FX Microprocessor Pinout Listings ...................................................................... 50

5. System Design Information ...................................................................................... 57

5.1 External Resistors .........................................................................................................................

5.2 PLL Configuration .........................................................................................................................

5.2.1 Determining PLLMULT and BUS_CFG Settings ...................................................................

5.2.2 PLL_RANGE Configuration ...................................................................................................

5.3 PLL Power Supply Filtering ..........................................................................................................

5.4 Decoupling Recommendations ....................................................................................................

5.4.1 Using the KVPRBVDD and KVPRBGND Pins .......................................................................

5.5 Decoupling Layout Guide .............................................................................................................

5.6 Input-Output Usage .......................................................................................................................

5.6.1 Chip Signal I/O and Test Pins ................................................................................................

5.7 Thermal Management Information ...............................................................................................

5.7.1 Thermal Management pins ....................................................................................................

5.7.2 Reading Thermal Diode Calibration data via JTAG ...............................................................

5.7.3 Heatsink Attachment and Mounting Forces ...........................................................................

5.8 Operational and Design Considerations .....................................................................................

5.8.1 Power-On Reset Considerations ...........................................................................................

5.8.2 Debugging PowerPC 970FX Power-On and Reset Sequence ..............................................

5.8.3 I

C Addressing of PowerPC 970FX .......................................................................................

Revision Log ................................................................................................................. 73

Page 4 of 74

October 14, 2005

Preliminary

Data Sheet

PowerPC 970FX

Figure 1-1. PowerPC 970FX Block Diagram ................................................................................................ 13

Figure 1-2. Part Number Legend .................................................................................................................. 16

Figure 3-1. Clock Differential HSTL Signal ................................................................................................... 24

Figure 3-2. Processor-Clock Timing Relationship Between PSYNC and SYSCLK ...................................... 25

Figure 3-3. Block Diagram of an SSB for a Processor Interconnect Implementation ................................... 26

Figure 3-4. Typical Implementation for a Single-ended Line ........................................................................ 27

Figure 3-5. Differential Clock Termination Circuitry ...................................................................................... 28

Figure 3-6. Post-IAP Eye Opening ............................................................................................................... 29

Figure 3-7. Asynchronous Input Timing ........................................................................................................ 31

Figure 3-8. HRESET and BYPASS Timing Diagram .................................................................................... 34

Figure 3-9. Spread Spectrum Clock Generator (SSCG) Modulation Profile ................................................. 36

Figure 3-10. JTAG Clock Input Timing Diagram ........................................................................................... 38

Figure 3-11. Test Access Port Timing Diagram ............................................................................................ 39

Figure 4-1. PowerPC 970FX Microprocessor for Mechanical Package, Leaded, for DD3.0x Parts (top and side)

Figure 4-2. PowerPC 970FX Microprocessor Mechanical Package, Leaded, for DD3.1x Parts (top and side)

Figure 4-3. PowerPC 970FX Microprocessor Bottom Surface Nomenclature of Mechanical Package, Leaded,

CBGA Package ............................................................................................................................................ 43

Figure 4-4. PowerPC 970FX Microprocessor for Mechanical Package, Reduced-Lead, for DD3.0x Parts (top

and side) ....................................................................................................................................................... 45

Figure 4-5. PowerPC 970FX Microprocessor Mechanical Package, Reduced-Lead, for DD3.1 Parts (top and

side) .............................................................................................................................................................. 46

Figure 4-6. PowerPC 970FX Microprocessor Bottom Surface Nomenclature of Reduced-Lead CBGA Package

Figure 4-7. PowerPC 970FX Ball Placement (Top View) ............................................................................. 48

Figure 4-8. PowerPC 970FX Ball Placement (Bottom View) ........................................................................ 49

Figure 5-1. PLL Power Supply Filter Circuit ................................................................................................. 60

Figure 5-2. Decoupling Capacitor (Decap) Locations ................................................................................... 62

Figure 5-3. PowerPC 970FX Thermal Diode Implementation ...................................................................... 70

Figure 5-4. Force Diagram for the PowerPC 970FX Package ..................................................................... 71

October 14, 2005

Page 5 of 74

参数对比

与IBM25PPC970FX6UB348RT相近的元器件有：IBM25PPC970FX6UR428ET、IBM25PPC970FX6TB348ET、IBM25PPC970FX6TR348ET、IBM25PPC970FX6TR348RT、IBM25PPC970FX6UR348RT、IBM25PPC970FX6TB348RT、IBM25PPC970FX6UR429RT、IBM25PPC970FX6UB429RT、IBM25PPC970FX6UB428ET。描述及对比如下：

型号	IBM25PPC970FX6UB348RT	IBM25PPC970FX6UR428ET	IBM25PPC970FX6TB348ET	IBM25PPC970FX6TR348ET	IBM25PPC970FX6TR348RT	IBM25PPC970FX6UR348RT	IBM25PPC970FX6TB348RT	IBM25PPC970FX6UR429RT	IBM25PPC970FX6UB429RT	IBM25PPC970FX6UB428ET
描述	RISC Microprocessor, 64-Bit, 2000MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576	RISC Microprocessor, 64-Bit, 2200MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-576	RISC Microprocessor, 64-Bit, 2000MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576	RISC Microprocessor, 64-Bit, 2000MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-576	RISC Microprocessor, 64-Bit, 2000MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-576	RISC Microprocessor, 64-Bit, 2000MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-576	RISC Microprocessor, 64-Bit, 2000MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576	RISC Microprocessor, 64-Bit, 2200MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, BGA-576	RISC Microprocessor, 64-Bit, 2200MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576	RISC Microprocessor, 64-Bit, 2200MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576
是否Rohs认证	不符合	符合	不符合	符合	符合	符合	不符合	符合	不符合	不符合
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576	BGA, BGA576,24X24,40	25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576	BGA, BGA576,24X24,40	BGA, BGA576,24X24,40	BGA, BGA576,24X24,40	25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576	BGA, BGA576,24X24,40	25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576	25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576
针数	576	576	576	576	576	576	576	576	576	576
Reach Compliance Code	not_compliant	unknown	not_compliant	not_compliant	not_compliant	unknown	not_compliant	unknown	not_compliant	not_compliant
ECCN代码	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
地址总线宽度	44	44	44	44	44	44	44	44	44	44
位大小	64	64	64	64	64	64	64	64	64	64
边界扫描	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
最大时钟频率	300 MHz	300 MHz	300 MHz	300 MHz	300 MHz	300 MHz	300 MHz	300 MHz	300 MHz	300 MHz
外部数据总线宽度	44	44	44	44	44	44	44	44	44	44
格式	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
集成缓存	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 代码	S-CBGA-B576	S-CBGA-B576	S-CBGA-B576	S-CBGA-B576	S-CBGA-B576	S-CBGA-B576	S-CBGA-B576	S-CBGA-B576	S-CBGA-B576	S-CBGA-B576
长度	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm
低功率模式	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
端子数量	576	576	576	576	576	576	576	576	576	576
封装主体材料	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
封装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
封装等效代码	BGA576,24X24,40	BGA576,24X24,40	BGA576,24X24,40	BGA576,24X24,40	BGA576,24X24,40	BGA576,24X24,40	BGA576,24X24,40	BGA576,24X24,40	BGA576,24X24,40	BGA576,24X24,40
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
电源	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.2 V	1.2 V	1.25 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	3.168 mm	2.808 mm	3.168 mm	2.808 mm	2.808 mm	2.808 mm	3.168 mm	2.808 mm	3.168 mm	3.168 mm
速度	2000 MHz	2200 MHz	2000 MHz	2000 MHz	2000 MHz	2000 MHz	2000 MHz	2200 MHz	2200 MHz	2200 MHz
最大供电电压	1.3 V	1.3 V	1.3 V	1.3 V	1.3 V	1.3 V	1.3 V	1.25 V	1.25 V	1.3 V
最小供电电压	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.2 V	1.15 V	1.15 V	1.2 V
标称供电电压	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.25 V	1.2 V	1.2 V	1.25 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
宽度	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm	25 mm
uPs/uCs/外围集成电路类型	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC
厂商名称	IBM	-	IBM	IBM	IBM	IBM	IBM	IBM	IBM	IBM