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IC42S16400A

Document Title

1M x 16Bit x 4 Banks (64-MBIT) SDRAM

Revision History

Revision No

History

Initial Draft

Draft Date

February 19,2004

Remark

The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and

products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.

Integrated Circuit Solution Inc.

DR039-0A 02/19/2004

IC42S16400A

1M x 16 Bits x 4 Banks (64-MBIT)

SYNCHRONOUS DYNAMIC RAM

FEATURES

• Single 3.3V (± 0.3V) power supply

• High speed clock cycle time -6: 166MHz,

-7: 133MHz<3-3-3>

• Fully synchronous operation referenced to clock

rising edge

• Possible to assert random column access in

every cycle

• Quad internal banks contorlled by A12 & A13

(Bank Select)

• Byte control by LDQM and UDQM for

IC42S16400A

• Programmable Wrap sequence (Sequential /

Interleave)

• Programmable burst length (1, 2, 4, 8 and full

page)

• Programmable

CAS

latency (2 and 3)

• Automatic precharge and controlled precharge

• CBR (Auto) refresh and self refresh

• LVTTL compatible inputs and outputs

• 4,096 refresh cycles / 64ms

• Burst termination by Burst stop and Precharge

command

• Package 400mil 54-pin TSOP-2 and 60ball(64M)

VF-BGA

• Pb(lead)-free package is available

DESCRIPTION

The IC42S16400A are high-speed 67,108,864-bit syn-

chronous dynamic random-access memories, orga-

nized as 1,048,576 x 16 x 4 (word x bit x bank),

respectively.

The synchronous DRAMs achieved high-speed data

transfer using the pipeline architecture and clock

frequency up to 166MHz for -6. All input and outputs are

synchronized with the positive edge of the clock.The

synchronous DRAMs are compatible with Low Voltage

TTL (LVTTL).These products are packaged in 54-pin

TSOP-2 and 60ball(64M) VF-BGA.

PIN CONFIGURATIONS

54-Pin TSOP-2

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

VDD

LDQM

CAS

RAS

BA0

BA1

A10

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

VSS

UDQM

CLK

CKE

A11

VSS

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

Integrated Circuit Solution Inc.

DR039-0A 02/19/2004

IC42S16400A

60-BALL VF-BGA ( 64M SDRAM )

VDD

A10

BA0

CAS

DQ7

DQ6

DQ5

DQ3

DQ2

DQ1

VDD

BA1

RAS

LDQM

VDD

VSSQ

VDDQ

DQ4

VSSQ

DDQ

DQ0

CLK

UDQM

VDDQ

VSSQ

VDDQ

VSSQ

VSS

A11

CKE

DQ8

DQ9

VSS

PIN DESCRIPTIONS

A0 - A11

BA0,BA1

DQ0 - DQ15

CLK

CKE

RAS

CAS

LDQM,UDQM

Q/V

Address

Bank Address

Data Input/Output

Clock

Clock Enable

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable

Data Input/Output Mask

Power Supply/Ground

Data Output Power/Ground

No Connection

Row Address : RA0 - RA11, Column Address : CA0 - CA7

Auto-precharge flag : A10

Selects bank to be activated during

RAS

activity

Selects bank to be read/written during

CAS

activity

Multiplexed data input / output pin

The system clock input.All other inputs are registered to the SDRAM

on the rising edge of CLK

Controls internal clock signal and when deactivated,the SDRAM will

be one of the states among power down,suspend or self refresh

Enables or disables all inputs except CLK, CKE and DQM

RAS,CAS

and

WE define the operation

Refer function truth table for details

Controls output buffers in read mode and masks input data in write

mode

Power supply for internal circuits and input buffers

Power supply for output buffers

No Connection

Integrated Circuit Solution Inc.

DR039-0A 02/19/2004

IC42S16400A

FUNCTIONAL BLOCK DIAGRAM

CLK

CKE

Clock

Generator

Address

Mode

Row Decoder

Row

Address

Buffer

Refresh

Counter

Bank D

Bank C

Bank B

Bank A

Sense Amplifier

Command Decoder

RAS

CAS

Control Logic

Input & Output

Buffer

Latch Circuit

Column

Address

Buffer

Burst

Counter

Column Decoder &

Latch Circuit

DQM

Data Control Circuit

Integrated Circuit Solution Inc.

DR039-0A 02/19/2004

IC42S16400A

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

DDQ

Parameters

Rating

Unit

°C

OPT

STG

Supply Voltage (with respect to V

)

–0.5 to +4.6

Supply Voltage for Output (with respect to V

SSQ

)

–0.5 to +4.6

Input Voltage

(with respect to V

)

–0.5 to V

+0.5

Output Voltage

(with respect to V

SSQ

)

–1.0 to V

DDQ

+0.5

Short circuit output current

Power Dissipation (

= 25 °C)

Operating Temperature

Storage Temperature

0 to +70

–65 to +150

Notes:

1. Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent

damage. The device is not meant to be operated under conditions outside the limits described in the

operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended

periods may affect device reliability.

DC RECOMMENDED OPERATING CONDITIONS

(

At T

= 0 to +70°C unless otherwise noted)

Symbol

DDQ

Parameter

Supply Voltage

Supply Voltage for DQ

High Level Input Voltage (all Inputs)

Low Level Input Voltage (all Inputs)

Min.

3.0

2.0

-0.3

Typ.

3.3

—

Max.

3.6

+ 0.3

+0.8

Unit

CAPACITANCE CHARACTERISTICS

(At T

= 0 ~ 70°C, V

= V

DDQ

= 3.3 ± 0.3V, V

= V

SSQ

= 0V , unless otherwise noted)

Symbol

CLK

Parameter

Input Capacitance, address & control pin

nput Capacitance, CLK pin

Min.

2.5

4.0

Max.

3.8

3.5

6.5

Unit

Data Input/Output Capacitance

Integrated Circuit Solution Inc.

DR039-0A 02/19/2004