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IC42S32202-6BI

512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

厂商名称：ISSI(芯成半导体)

厂商官网：http://www.issi.com/

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IC42S32202/L
Document Title
512K x 32 Bit x 4 Banks (64-MBIT) SDRAM
Revision History
Revision No
0A
History
Initial Draft
Draft Date
August 17,2004
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004
1
IC42S32202/L
512K Words x 32 Bits x 4 Banks (64-MBIT)
SYNCHRONOUS DYNAMIC RAM
FEATURES
· Concurrent auto precharge
· Clock rate:166/143/125 MHz
· Fully synchronous operation
· Internal pipelined architecture
· Four internal banks (512K x 32bit x 4bank)
· Programmable Mode
-CAS#Latency:2 or 3
-Burst Length:1,2,4,8,or full page
-Burst Type:interleaved or linear burst
-Burst-Read-Single-Write
· Burst stop function
· Individual byte controlled by DQM0-3
· Auto Refresh and Self Refresh
· 4096 refresh cycles/64ms
· Single +3.3V ±0.3V power supply
· Interface:LVTTL
· Package:400 x 875 mil,86 Pin TSOP-2,0.50mm Pin
Pitch and 11x13mm, 90 Ball BGA, Ball pitch 0.8mm
· Pb-free package is available.
DESCRIPTION
The
ICSI
IC42S32202 and IC42S32202L is a high-speed
CMOS configured as a quad 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal,CLK).
Each of the 512K x 32 bit banks is organized as 2048 rows
by 256 columns by 32 bits.Read and write accesses start
at a selected locations in a programmed sequence.
Accesses begin with the registration of a BankActive
command which is then followed by a Read or Write
command
The
ICSI
IC42S32202 and IC42S32202L provides for
programmable Read or Write burst lengths of 1,2,4,8,or
full page, with a burst termination operation. An auto
precharge function may be enable to provide a self-timed
row precharge that is initiated at the end of the burst
sequence.The refresh functions,either Auto or Self
Refresh are easy to use.
By having a programmable mode register,the system
can choose the most suitable modes to maximize its
performance.
These devices are well suited for applications requiring
high memory bandwidth.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004
IC42S32202/L
FUNCTIONAL BLOCK DIAGRAM
Column Decoder
Row Decoder
2048 X 256 X 32
C E L L A R R AY
(BANK #0)
Sense
Amplifier
CLK
CLOCK
BUFFER
CONTROL
SIGNAL
G E N E R AT O R
CKE
Sense
CS#
RAS#
CAS#
WE#
Row Decoder
Amplifier
COMMAND
DECODER
MODE
REGISTER
2048 X 256 X 32
C E L L A R R AY
(BANK #1)
Col um n
Decoder
COLUMN
C O U N TE R
A10/AP
Column Decoder
Row Decoder
A0
A9
BS0
BS1
ADDRESS
BUFFER
2048 X 256 X 32
CELL ARRAY
(BANK #2)
Sense Amplifier
REFRESH
COUNTER
Sense
DQ
BUFFER
DQ0
D Q 31
Decoder
Amplifier
Row
2048 X 256 X 32
CELL ARRAY
(BANK #3)
Column
Decoder
DQM0~3
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004
3
IC42S32202/L
PIN DESCRIPTIONS
Table 1.Pin Details of IC42S32202 and IC42S32202L
Symbol Type
Description
CLK
CKE
Input
Input
Clock:CLK
is driven by the system clock.All SDRAM input signals are sampled on the positive edge
of CLK.CLK also increments the internal burst counter and controls the output registers.
Clock Enable:CKE
activates(HIGH)and deactivates(LOW)the CLK signal.If CKE goes low syn-
chronously with clock(set-up and hold time same as other inputs),the internal clock is suspended
from the next clock cycle and the state of output and burst address is frozen as long as the CKE
remains low.When all banks are in the idle state,deactivating the clock controls the entry to the
Power Down and Self Refresh modes.CKE is synchronous except after the device enters Power
Down and Self Refresh modes,where CKE becomes asynchronous until exiting the same mode.
The input buffers,including CLK,are disabled during Power Down and Self Refresh modes,providing
low standby power.
Bank Select:BS0
and BS1 defines to which bank the BankActivate,Read,Write,or BankPrecharge
command is being applied.
Address Inputs:A0-A10
are sampled during the BankActivate command (row address A0-A10)and
Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one
location out of the 256K available in the respective bank.During a Precharge command,A10 is
sampled to determine if all banks are to be precharged (A10 =HIGH).
The address inputs also provide the op-code during a Mode Register Set .
BS0,BS1 Input
A0-A10 Input
CS#
Input
Chip Select:CS#enables
(sampled LOW)and disables (sampled HIGH)the command decoder.All
commands are masked when CS#is sampled HIGH.CS#provides for external bank selection on
systems with multiple banks.It is considered part of the command code.
Row Address Strobe:The
RAS#signal defines the operation commands in conjunction with the
CAS#and WE#signals and is latched at the positive edges of CLK.When RAS# and CS#are as-
serted “LOW”and CAS#is asserted “HIGH,”either the BankActivate command or the Precharge
command is selected by the WE#signal.When the WE#is asserted “HIGH,”the BankActivate com-
mand is selected and the bank designated by BS is turned on to the active state.When the WE#is
asserted “LOW,”the Precharge command is selected and the bank designated by BS is switched to
the idle state after the precharge operation.
Column Address Strobe:The
CAS#signal defines the operation commands in conjunction with the
RAS#and WE#signals and is latched at the positive edges of CLK. When RAS#is held “HIGH”and
CS#is asserted “LOW,”the column access is started by asserting CAS#”LOW.”Then,the Read or
Write command is selected by asserting WE# “LOW”or “HIGH.”
Write Enable:The
WE#signal defines the operation commands in conjunction with the RAS#and
CAS#signals and is latched at the positive edges of CLK.The WE#input is used to select the
BankActivate or Precharge command and Read or Write command.
Data Input/Output Mask:DQM0-DQM3
are byte specific,nonpersistent I/O buffer controls. The I/O
buffers are placed in a high-z state when DQM is sampled HIGH.Input data is masked when DQM
is sampled HIGH during a write cycle.Output data is masked (two-clock latency)when DQM is
sampled HIGH during a read cycle.DQM3 masks DQ31-DQ24,DQM2 masks DQ23-DQ16,DQM1
masks DQ15-DQ8,and DQM0 masks DQ7-DQ0.
RAS#
Input
CAS#
Input
WE#
Input
DQM0-3 Input
DQ0-31 Input/Output Data I/O:The
DQ0-31 input and output data are synchronized with the positive edges of
CLK.The I/Os are byte-maskable during Reads and Writes.
4
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004
IC42S32202/L
PIN FUNCTION
NC
VDDQ
VSSQ
VDD
VSS
-
Supply
Supply
Supply
Supply
No Connect:These
pins should be left unconnected.
DQ Power:Provide
isolated power to DQs for improved noise immunity.
DQ Ground:Provide
isolated ground to DQs for improved noise immunity.
Power Supply:+3.3V
± 0.3V
Ground
PIN CONFIGURATIONS
86-Pin TSOP 2
Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM 0
/WE
/CAS
/RAS
/CS
NC
BS0
BS1
A10/AP
A0
A1
A2
DQM 2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CL K
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
90-Ball FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
DQ
26
DQ
28
V
SSQ
V
SSQ
V
DDQ
V
SS
A4
A7
CLK
DQM1
V
DDQ
V
SSQ
V
SSQ
DQ11
DQ13
2
DQ
24
V
DDQ
DQ
27
DQ
29
DQ
31
DQM
3
A5
A8
CKE
NC
DQ
8
DQ
10
DQ
12
V
DDQ
DQ
15
3
Vss
V
SSQ
DQ
25
DQ
30
NC
A3
A6
4
5
6
7
V
DD
V
DDQ
DQ
22
DQ
17
NC
A2
A10
8
DQ
23
V
SSQ
DQ
20
DQ
18
DQ
16
DQM
2
A0
BA1
CS
WE
DQ
7
DQ
5
DQ
3
V
SSQ
DQ
0
9
DQ
21
DQ
19
V
DDQ
V
DDQ
V
SSQ
V
DD
A1
NC
RAS
DQM
0
V
SSQ
V
DDQ
V
DDQ
DQ
4
DQ
2
(Top View)
NC
A9
NC
V
SS
DQ
9
DQ
14
V
SSQ
V
SS
NC
BA0
CAS
V
DD
DQ
6
DQ
1
V
DDQ
V
DD
Integrated Circuit Solution Inc.
DR042-0C 08/17/2004
5
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