IC61C256AH
Document Title
32K x 8 High Speed SRAM
Revision History
Revision No
0A
0B
0C
0D
History
Initial Draft
Revise typo of t
HA
on page 7
Add SOP package type
Revise typo of sop size at page 2,9
Draft Date
March 23,2001
October 18,2001
February 18,2002
April 19,2002
Remark
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
AHSR010-0D 4/19/2002
1
IC61C256AH
32K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access times: 10, 12, 15, 20, 25 ns
• Low active power: 400 mW (typical)
• Low standby power
-- 250
µW
(typical) CMOS standby
-- 55 mW (typical) TTL standby
• Fully static operation: no clock or refresh
required
• TTL compatible interface and outputs
• Single 5V power supply
DESCRIPTION
The
ICSI
IC61C256AH is very high-speed, low power, 32,768
word by 8-bit static RAMs. They are fabricated using
ICSI
's
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 8 ns maximum.
When
CE
is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50
µ
W (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IC61C256AH is pin compatible with other 32k x
8
SRAMs
and are available in 28-pin 300mil PDIP, 300mil SOJ, and
8*13.4mm TSOP-1 package, 330 mil SOP.
FUNCTIONAL BLOCK DIAGRAM
A0-A14
DECODER
32K X 8
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
AHSR010-0D 4/19/2002
IC61C256AH
PIN CONFIGURATION
28-Pin DIP and SOJ and SOP
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
PIN CONFIGURATION
8x13.4mm TSOP-1
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PIN DESCRIPTIONS
A0-A14
CE
OE
WE
I/O0-I/O7
Vcc
GND
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Input/Output
Power
Ground
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O Operation
High-Z
High-Z
D
OUT
D
IN
Vcc Current
I
SB
1
, I
SB
2
I
CC
1
,I
CC
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
D
I
OUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–55 to +125
–65 to +150
1.5
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Integrated Circuit Solution Inc.
AHSR010-0D 4/19/2002
3
IC61C256AH
OPERATING RANGE
Range
Commercial
Industrial
Notes:
1. 8 ns is preliminary.
Ambient Temperature
0°C to +70°C
–40°C to +85°C
Speed
-10, -12
-15, -20
-12
-15, -20, -25
V
CC
5V, ± 5%
5V ± 10%
5V ± 5%
5V± 10%
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(1)
Input LOW Voltage
(2)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
,
Outputs Disabled
Com.
Ind.
Com.
Ind.
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.2
–0.5
–5
–10
–5
–10
Max.
—
0.4
V
CC
+ 0.5
0.8
5
10
5
10
Unit
V
V
V
V
µA
µA
Notes:
1. V
IH
=V
CC
+3.0V for pulse width less than 10ns.
2. V
IL
= –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-10
Sym. Parameter
I
CC
I
SB
1
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥V
IH
, f = 0
V
CC
= Max.,
CE
≥
V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
Min. Max.
-12
Min. Max.
-15
Min. Max.
-20
Min. Max.
-25
Min. Max.
Unit
— 145
— 180
— 25
— 30
— 2
— 10
— 135
— 170
— 25
— 30
— 2
— 10
— 125
— 160
— 25
— 30
— 2
— 10
— 120
— 150
— 25
— 30
— 2
— 10
— 120
— 140
— 25
— 30
— 2
— 10
mA
mA
I
SB
2
mA
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
8
10
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 5V.
4
Integrated Circuit Solution Inc.
AHSR010-0D 4/19/2002
IC61C256AH
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
-10
Symbol Parameter
Min.
Max.
Min.
-12
Max.
Min.
-15
Max.
Min.
-20
Max.
Min.
-25
Max.
Unit
t
RC
t
OHA
t
ACE
t
DOE
Read Cycle Time
Output Hold Time
CE
Access Time
OE
Access Time
10
—
2
—
—
0
—
2
—
0
—
—
10
—
10
5
—
5
—
5
—
10
12
—
2
—
—
0
—
3
—
0
—
—
12
—
12
5
—
6
—
7
—
12
15
—
2
—
—
0
—
3
—
0
—
—
15
—
15
7
—
7
—
8
—
15
20
—
2
—
—
0
—
3
—
0
—
—
20
—
20
8
—
9
—
9
—
18
25
—
2
—
—
0
—
3
—
0
—
—
25
—
25
9
—
10
—
10
—
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AA
Address Access Time
t
LZOE
(2)
OE
to Low-Z Output
t
HZOE
(2)
OE
to High-Z Output
t
LZCE
(2)
CE
to Low-Z Output
t
HZCE
(2)
CE
to High-Z Output
t
PU
(3)
CE
to Power-Up
t
PD
(3)
CE
to Power-Down
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
480
Ω
5V
5V
480
Ω
OUTPUT
30 pF
Including
jig and
scope
255
Ω
OUTPUT
5 pF
Including
jig and
scope
255
Ω
Figure 1.
Integrated Circuit Solution Inc.
AHSR010-0D 4/19/2002
Figure 2.
5
