The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
SSR019-0A
09/17/2001
1
IC61SP12832
IC61SP12836
128K x 32, 128K x 36 SYNCHRONOUS
PIPELINED STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• 100-Pin TQFP (JEDEC LQFP) and
119-pin PBGA package
• Single +3.3V, +10%, –5% power supply
• Power-down snooze mode
DESCRIPTION
The
ICSI
IC61SP12832,IC61SP12836 are high-speed, low-
power synchronous static RAM designed to provide a burstable,
high-performance, secondary cache for the Pentium™, 680X0™,
and PowerPC™ microprocessors. It is organized as 131,072
words by 32 bits, fabricated with
ICSI
's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1
controls DQa,
BW2
controls DQb,
BW3
controls DQc,
BW4
controls DQd, conditioned by
BWE
being LOW. A LOW
on
GW
input would cause all bytes to be written.
Bursts can be initiated with either
ADSP
(Address Status
Processor) or
ADSC
(Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IC61SP12832,IC61SP12836 and controlled by the
ADV
(burst address advance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
t
KQ
t
KC
Parameter
Clock Access Time
Cycle Time
Frenquency
-166
3.5
6
166
-150
3.8
6.7
150
-133
4
7.5
133
-117
4
8.5
117
-5
5
10
100
Units
ns
ns
MHz
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
