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IC62LV1008LL-100DI

1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM

厂商名称:Integrated Circuit Solution Inc

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IC62LV1008L
IC62LV1008LL
Document Title
1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
0A
History
Initial Draft
Draft Date
January 3,2002
Remark
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2002
1
IC62LV1008L
IC62LV1008LL
1M x 8 LOW POWER and LOW V
CC
CMOS STATIC RAM
FEATURES
• Access times of 55, 70, 100 ns
• CMOS Low power operation:
I
CC
=15mA (typical)* operation
I
SB2
=2
µA
(typical)* standby
• Low data retention voltage: 1.5V (min.)
• Output Enable (OE) and Two Chip Enables
(CE1, CE2) inputs for ease in applications
• TTL compatible inputs and outputs
• Fully static operation:
No clock or refresh reguired
• Single 2.7V-3.6V power supply
• Wafer level burn in test mode
• Available in the know good die form and
48-pin 8*10mm TF-BGA
* Typical values are measured at V
CC
=3.0V, T
A
=25°C
Preliminary
DESCRIPTION
The
ICSI
IC62LV1008L and IC62LV1008LL is a low voltage,
1,048,576 words by 8 bits, CMOS SRAM. It is fabricated using
ICSI
's low voltage, six transistor (6T), CMOS technology. The
device is targeted to satisfy the demands of the state-of-the-art
technologies such as cell phones and pagers.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced down with CMOS input levels. Additionally, easy
memory expansion is provided by using two Chip Enable
inputs,
CE1
and CE2. The active LOW Write Enable (
WE)
controls both writing and reading of the memory.
The IC62LV1008L and IC62LV1008LL are available in know
good die form and 48-pin 8*10mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A19
DECODER
1024K x 8
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1
CE2
OE
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
CONTROL
CIRCUIT
2
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
PIN CONFIGURATIONS
48-Pin 8*10mm TF-BGA (TOP View)
1
A
B
C
D
E
F
G
H
NC
NC
I/O
0
GND
Vcc
I/O
3
NC
A18
2
OE
NC
NC
I/O
1
I/O
2
NC
NC
A8
3
A0
A3
A5
A17
Vcc
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE1
NC
I/O
5
I/O
6
NC
WE
A11
6
CE2
NC
I/O
4
Vcc
GND
I/O
7
NC
A19
PIN DESCRIPTIONS
A0-A19
CE1
CE2
OE
WE
I/O0-I/O7
NC
Vcc
GND
Address Inputs
Chip Enable 1 Input
Chip Enable 2 Input
Output Enable Input
Write Enable Input
Data Input/Output
No Connection
Power
Ground
TRUTH TABLE
Mode
Not Selected
(P
OWER
-D
OWN
)
Output Disabled
Read
Write
WE
X
X
H
H
L
CE1
H
X
L
L
L
CE2
X
L
H
H
H
OE
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
D
OUT
D
IN
Vcc Current
I
SB
1
, I
SB
2
I
SB
1
, I
SB
2
I
CC
I
CC
I
CC
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
2.7V - 3.6V
2.7V - 3.6V
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2002
3
IC62LV1008L
IC62LV1008LL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
V
CC
T
BIAS
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Vcc related to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc + 0.5
–0.3 to +4.0
–40 to +85
–65 to +150
1
Unit
V
V
°C
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE
(1)(2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25
o
C, f = 1 MHz, V
CC
= 3.0 V
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(1)
Input LOW Voltage
(2)
Input Leakage
Output Leakage
Test Conditions
V
CC
= Min., I
OH
= –1.0 mA
V
CC
= Min., I
OL
= 2.1 mA
Min.
2.0
2.2
–0.2
–1
–1
Max.
0.4
V
CC
+ 0.3
0.4
1
1
Unit
V
V
V
V
µA
µA
GND
V
IN
V
CC
GND
V
OUT
V
CC
Notes:
1. V
IH(max.)
= V
CC
+2.0V for pulse width less than 10 ns.
1. V
IL(min.)
= –2.0V for pulse width less than 10 ns.
4
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2001
IC62LV1008L
IC62LV1008LL
IC62LV1008L POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-55
Symbol Parameter
I
CC
I
SB
1
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= 3.0V, CE1 = V
IL
,CE2=V
IH
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max., f = 0
CE1
V
IH
or CE2
V
IL
,
V
IN
= V
IH
or V
IL
,
V
CC
= Max., f = 0
CE1
V
CC
– 0.2V
or CE2
0.2V,
V
IN
V
CC
– 0.2V, V
IN
0.2V
Com.
Ind.
Com.
Ind.
Com.
Ind.
Min.
Max. Min.
30
35
0.2
0.3
35
50
-70
Max. Min.
25
30
-100
Max. Unit
20
25
0.2
0.3
35
50
mA
mA
0.2 —
0.3 —
35
50
I
SB
2
µA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IC62LV1008LL POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
-55
Symbol Parameter
I
CC
I
SB
1
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
CC
= 3.0V, CE1 = V
IL
,CE2=V
IH
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max., f = 0
CE1
V
IH
or CE2
V
IL
,
V
IN
= V
IH
or V
IL
,
V
CC
= Max., f = 0
CE1
V
CC
– 0.2V
or CE2
0.2V,
V
IN
V
CC
– 0.2V, V
IN
0.2V
Com.
Ind.
Com.
Ind.
Com.
Ind.
Min.
Max. Min.
30
35
0.2
0.3
20
25
-70
Max. Min.
25
30
-100
Max. Unit
20
25
0.2
0.3
20
25
mA
mA
0.2 —
0.3 —
20
25
I
SB
2
µA
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Circuit Solution Inc.
LPSR015-0A 1/3/2002
5
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