IC62LV12816L
IC62LV12816LL
IC62LV12816L
IC62LV12816LL
128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
.EATURES
High-speed access times: 55, 70, 100 ns
CMOS low power operation
-- 60 mW (typical) operating
-- 3 µW (typical) CMOS standby
TTL compatible interface levels
Single 2.7V-3.6V Vcc power supply
.ully static operation: no clock or refresh re-
quired
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Available in the 44-pin TSOP-2 and 48-pin
6*8mm T.-BGA
DESCRIPTION
The
1+51
IC62LV12816L and IC62LV12816LL are high-speed,
2.097,152-bit static RAMs organized as 131,072 words by 16
bits. They are fabricated using
1+51
's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields high-performance and
low power consumption devices.
When
CE
is HIGH (deselected) or when
CE
is low and both
LB
and
UB
are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced by using CMOS
input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs,
CE
and
OE.
The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IC62LV12816L and IC62LV12816LL are packaged in the
JEDEC standare 44-pin 400mil TSOP-2 and 48-pin 6*8mm
T.-BGA.
.UNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
UB
LB
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
1
IC62LV12816L
IC62LV12816LL
PIN CON.IGURATIONS
44-Pin TSOP-2
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
Vcc
GND
I/O4
I/O5
I/O6
I/O7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
48-Pin T.-BGA
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
Vcc
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
1
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
GND
Vcc
I/O
14
I/O
15
NC
2
OE
UB
I/O
10
I/O
11
I/O
12
I/O
13
NC
A8
3
A0
A3
A5
NC
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A11
6
N/C
I/O
0
I/O
2
Vcc
GND
I/O
6
I/O
7
NC
PIN DESCRIPTIONS
A0-A16
I/O0-I/O15
CE
OE
WE
Address Inputs
Data Input/Output
Chip Enable Input
Output Enable Input
Write Enable Input
LB
UB
NC
Vcc
GND
Lower-byte Control (l/O0-I/O7)
Upper-byte Control (l/O8-I/O15)
No Connection
Power
Ground
TRUTH TABLE
Mode
Not Selected
WE
CE
H
L
L
L
L
L
L
L
L
L
OE
X
X
H
X
L
L
L
X
X
X
LB
X
H
X
H
L
H
L
L
H
L
UB
X
H
X
H
H
L
L
H
L
L
I/O PIN
I/O0/-I/O7
I/O8-I/O15
High-Z
High-Z
High-Z
High-Z
D
OUT
High-Z
D
OUT
D
IN
High-Z
D
IN
High-Z
High-Z
High-Z
High-Z
High-Z
D
OUT
D
OUT
High-Z
D
IN
D
IN
Vcc Current
I
SB
, I
SB
I
SB
, I
SB
I
CC
I
SB
I
CC
X
X
Output Disabled H
X
Read
H
H
H
Write
L
L
L
I
CC
2
Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
40°C to +85°C
V
CC
2.7V - 3.6V
2.7V - 3.6V
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
V
CC
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Vcc related to GND
Storage Temperature
Power Dissipation
Value
0.5 to Vcc + 0.5
40 to +85
0.3 to +4.0
65 to +150
1.0
Unit
V
°C
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
V
CC
= Min., I
OH
= 1 mA
V
CC
= Min., I
OL
= 2.1 mA
Min.
2.0
2.2
0.2
1
1
Max.
0.4
V
CC
+ 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
GND
£
V
IN
£
V
CC
GND
£
V
OUT
£
V
CC
, O
UTPUTS
D
ISABLED
Notes:
1. V
IL
(min.) = 2.0V for pulse width less than 10 ns.
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
p.
p.
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
3
IC62LV12816L
IC62LV12816LL
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and .all Times
Input and Output Timing
and Reference Level
Output Load
Unit
0.4V to 2.2V
5 ns
1.3V
See .igures 1 and 2
AC TEST LOADS
1 TTL
OUTPUT
100 pF
Including
jig and
scope
OUTPUT
5 pF
Including
jig and
scope
1 TTL
.igure 1
.igure 2
IC62LV12816L POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
OR
ULB Control
I
SB
CMOS Standby
Current (CMOS Inputs)
OR
ULB Control
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
V
IN
= V
IH
or V
IL
,
CE
£
V
IH
, f = 0
Com.
Ind.
Com.
Ind.
-55
Min. Max.
40
45
0.5
1.0
-70
Min. Max.
30
35
0.5
1.0
-100
Min. Max.
20
25
0.5
1.0
Unit
mA
mA
V
CC
= Max., V
IN
= V
IH
or V
IL
CE
=
V
IL
, f = 0,
UB
=
V
IH
,
LB
=
V
IH
V
CC
= Max.,
CE
³
V
CC
0.2V,
V
IN
³
V
CC
0.2V, or
V
IN
£
0.2V, f = 0
Com.
Ind.
35
50
35
50
35
50
µA
V
CC
= Max.,
CE
=
V
IL
V
IN
£
0.2V, f = 0,
UB
/
LB
=
V
CC
0.2V
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
IC62LV12816L
IC62LV12816LL
IC62LV12816LL POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
I
SB
Vcc Dynamic Operating
Supply Current
TTL Standby Current
(TTL Inputs)
OR
ULB Control
I
SB
CMOS Standby
Current (CMOS Inputs)
OR
ULB Control
Test Conditions
V
CC
= Max.,
I
OUT
= 0 mA, f = f
MAX
V
CC
= Max.,
V
IN
= V
IH
or V
IL
,
CE
³
V
IH
, f = 0
Com.
Ind.
Com.
Ind.
-55
Min. Max.
40
45
0.5
1.0
-70
Min. Max.
30
35
0.5
1.0
-100
Min. Max.
20
25
0.5
1.0
Unit
mA
mA
V
CC
= Max., V
IN
= V
IH
or V
IL
CE
=
V
IL
, f = 0,
UB
=
V
IH
,
LB
=
V
IH
V
CC
= Max., f = 0
CE
³
V
CC
0.2V,
V
IN
³
V
CC
0.2V, or
V
IN
£
0.2V, f = 0
Com.
Ind.
10
15
10
15
10
15
µA
V
CC
= Max.,
CE
=
V
IL
V
IN
£
0.2V, f = 0,
UB
/
LB
=
V
CC
0.2V
Note:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
Min.
55
10
5
0
10
0
0
-55
Max.
55
55
30
20
20
55
25
Min.
70
10
5
0
10
0
0
-70
Max.
70
70
35
25
25
70
25
-100
Min. Max.
100
15
5
0
10
0
0
100
100
50
30
30
100
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
HZOE
OE
to High-Z Output
t
LZOE
OE
to Low-Z Output
t
HZCE
CE
to High-Z Output
t
LZCE
CE
to Low-Z Output
t
BA
t
HZB
t
LZB
LB, UB
Access Time
LB, UB
o High-Z Output
LB. UB
to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels
of 0.4V to 2.2V and output loading specified in .igure 1.
2. Tested with the load in .igure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Circuit Solution Inc.
LPSR011-0B 06/06/2001
5
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