512 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM
Revision History
Revision No
0A
0B
History
Draft Date
Remark
Initial Draft
January 3,2002
1. Add CE2 pin for 48 pin TF-BGA
September 2,2002
2. Change for I
CC
: 35 mA to 30 mA for 55 ns Industrial product
30 mA to 25 mA for 70 ns Industrial product
25 mA to 20 mA for 100 ns Industrial product
30 mA to 25 mA for 55 ns Commerical product
25 mA to 20 mA for 70 ns Commerical product
20 mA to 15 mA for 100 ns Commerical product
3. Change for I
SB
2
: 20 µA to 15 µA for Commerical product
4. Change for I
DR
: 15 µA to 20 µA for Commerical/L product
6 µA to 13 µA for Commerical/LL product
20 µA to 30 µA for Industrial/L product
9 µA to 23 µA for Industrial/LL product
1. Revise typo for pin assignment H1 from NC to A18
January 22,2003
2. Change Truth Table of LB/UB control,CE1 and CE2 to "Don't care"
3. Change DC parameters for TSOP-2 package as follows
(1)V
IH :
2.2V to 2.8V
(2)I
SB
1 : 0.2mA to 0.7mA for commercial product
0.3mA to 0.8mA for Industrial product
(3)I
SB
2 : 15µA to 20µA for commercial/LL product
25µA to 30µA for Industrial/LL product
(4)I
CC
: 25mA to 30mA for commercial/LL product
30mA to 35mA for Industrial/LL product
0C
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
LPSR014-0C 1/22/2003
1
IC62LV51216L
IC62LV51216LL
512K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
• High-speed access times: 55, 70, 100 ns
•
CMOS low power operation
I
CC
=18mA (typical)* operating
I
SB2
=3
µA
(typical)* CMOS standby
• TTL compatible interface levels
• Single 2.7V-3.6V Vcc power supply
• Fully static operation: no clock or refresh re-
quired
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the know good die from 44-pin
TSOP-2 and 48-pin 8x10mm TF-BGA
• CE2 pin only for 48-pin TF-BGA.
* Typical values are measured at V
CC
=3.0V, T
A
=25°C
DESCRIPTION
The
ICSI
IC62LV51216L and IC62LV51216LL are low-power,
8.388,608 bit static RAMs organized as 524,288 words by 16
bits. They are fabricated using
ICSI
's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields high-performance and
low power consumption devices.
When CE1 is HIGH or when CE2 is low (deselected) or both
LB
and
UB
are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced by using CMOS
input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE1, CE2 and
OE.
The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower Byte
(LB) access.
The IC62LV51216L and IC62LV51216LL are packaged in the
JEDEC standare 44-pin TSOP-2 and 48-pin 8*10mm TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A18
DECODER
512K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE1/ CE2
OE
WE
UB
LB
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
