Analog Input Voltage (either input) (Note 1)................... V+ to V-
Reference Input Voltage (either input) .......................... V+ to V-
Clock Input ..................................................................Gnd to V+
Note 1:
Input voltages may exceed the supply voltages provided the input current is limited to +100µA.
Note 2:
Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ICL7135 Electrical Characteristics
(Note 1)
CHARACTERISTICS
Zero Input Reading
Ratiometric Reading (Note 2)
Linearity over ± Full Scale
(Error of Reading from Best Straight Line)
ANALOG
(Note 1)
(Note 2)
Differential Linearity (Difference Between Worst-
Case Step of Adjacent Counts and Ideal Step)
Rollover error (Difference in Reading for Equal
Positive and Negative Voltage Near Full Scale)
Noise (P-P Value Not Exceeded 95% of Time)
Leakage Current at Input
Zero Reading Drift
Scale Factor Temperature
Coefficient (Note 3)
(V+ = +5V, V- = -5V, T
A
= 25°C, Clock Frequency Set for 3 Reading/Sec)
SYMBOL
CONDITIONS
V
IN
= 0.0V
Full Scale = 2.000V
V
IN
= V
REF
Full Scale = 2.000V
-2V ≤ V
IN
≤ +2V
-2V ≤ V
IN
≤ +2V
-V
IN
≡ V
IN
≈ 2V
en
I
ILK
V
IN
= 0V
Full Scale = 2.000V
V
IN
= 0V
V
IN
= 0V
0° ≤ T
A
≤ +70°C
TC
V
INH
INPUTS
Clock In, Run/Hold
V
INL
I
INL
I
INH
All Outputs
OUTPUTS
DIGITAL
B
1
, B
2
, B
4
, B
8
D
1
, D
2
, D
3
, D
4
, D
5
BUSY,
STROBE,
OVER-RANGE,
UNDER-RANGE, POLARITY
+5V Supply Range
-5V Supply Range
SUPPLY
+5V Supply Current
-5V Supply Current
Power Dissipation Capacitance
Clock
Clock Frequency (Note 4)
V
OL
V
OH
V
OH
V+
V-
I+
I-
C
PD
f
C
= 0
f
C
= 0
vs. Clock Freq
DC
V
IN
= 0V
V
IN
= +5V
I
OL
= 1.6mA
I
OH
= -1mA
I
OH
= -10µA
2.4
4.9
+4
-3
V
IN
= +2V
0° ≤ T
A
≤ +70°C
(ext. ref. 0 ppm/°C)
2.8
MIN
-0.0000
+0.9995
TYP
±0.0000
+0.9999
0.5
.01
0.5
15
1
0.5
10
2
1
MAX
+0.0000
+1.0000
1
UNITS
Digital
Reading
Digital
Reading
Digital
Count Error
LSB
Digital
Count Error
µV
pA
µV/°C
2
2.2
1.6
0.02
0.1
0.25
4.2
4.99
+5
-5
1.1
0.8
40
2000
5
ppm/°C
V
0.8
0.1
10
0.40
mA
µA
V
V
V
+6
-8
3.0
3.0
1200
V
V
mA
pF
kHz
Note 1:
Tested in 4
1
/
2
digit (20,000 count) circuit shown in Figure 1, clock frequency 120kHz.
Note 2:
Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.
Note 3:
The temperature range can be extended to +70°C and beyond as long as the auto-zero and reference capacitors are
increased to absorb the higher leakage of the ICL7135.
Note 4:
This specification relates to the clock frequency range over which the ICL7135 will correctly perform its various functions.
See “Max Clock Frequency” below for limitations on the clock frequency range in a system.
The electrical characteristics above are a reproduction of a portion of lntersil’s copyrighted (1983/1984) data book. This information does not constitute
any representation by Maxim that Intersil’s products will perform in accordance with these specifications. The “Electrical Characteristics Table” along
with the descriptive excerpts from the original manufacturer’s data sheet have been included in this data sheet solely for comparative purposes.
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Maxim Integrated
│
2
ICL7135
4
1
/
2
Digit A/D Converter with
Multiplexed BCD Outputs
●
Significantly Improved ESD Protection (Note 6)
●
Guaranteed 2mA Max Supply Current
●
Key Parameters Guaranteed Over Temperature
●
Low Noise
●
Maxim Quality and Reliability
Absolute Maximum Ratings:
This device conforms to the Absolute Maximum Ratings on adjacent page.
Electrical Characteristics
Specifications below satisfy or exceed all ‘’tested” parameters on adjacent page.
(V+ = +5V, V- = -5V, T
A
= +25°C, Clock Frequency Set for 3 Reading/Sec)
CHARACTERISTICS
Zero Input Reading
Ratiometric Reading (Note 2)
Linearity Over ± Full Scale
(Error of Reading from Best
Straight Line)
ANALOG
(Note 1)
(Note 2)
Differential Linearity (Difference
Between Worst-Case Step of
Adjacent Counts and Ideal Step)
Rollover Error (Difference in
Reading for Equal Positive and
Negative Voltage Near Full Scale)
Noise (P-P value not exceeded
95% of time)
Leakage Current at Input
Zero Reading Drift
Scale Factor Temperature
Coefficient (3)
TC
V
INH
INPUTS
Clock In, Run/Hold
V
INL
I
INL
I
INH
All Outputs
OUTPUTS
B
1
, B
2
, B
4
, B
8
D
1
, D
2
, D
3
, D
4
, D
5
BUSY,
STROBE
,
OVER-RANGE,
UNDER-RANGE POLARITY
+5V Supply Range
-5V Supply Range
SUPPLY
+5V Supply Current
-5V Supply Current
Power Dissipation Capacitance
CLOCK
Clock Frequency (Note 4)
V
OL
V
OH
V
OH
V+
V-
I+
I-
C
PD
f
C
= 0
f
C
= 0
(Note 5)
DC
T
A
= 25°C
0° ≤ T
A
≤ +70°C
T
A
= 25°C
0° ≤ T
A
≤ +70°C
V
IN
= 0V
V
IN
= +5V
I
OL
= 1.6mA
I
OH
= -1mA
I
OH
= -10µA
2.4
4.9
+4
-3
SYMBOL
CONDITIONS
V
IN
= 0.0V, Full Scale = 2.000V
0° ≤ T
A
≤ +70°C
V
IN
= V
REF
, Full Scale = 2.000V
T
A
= 25°C
0° ≤ T
A
≤ +70°C
-2V ≤ V
IN
≤ +2V
MIN
-0.0000
+0.9998
+0.9995
TYP
±0.0000
+0.9999
+0.9999
0.5
MAX
-0.0000
+1.0000
+1.0005
1
UNITS
Digital
Reading
Digital
Reading
Digital
Count Error
LSB
Digital
Count Error
µV
10
250
2
2.8
2.2
1.6
0.02
0.1
0.25
4.2
4.99
+5
-5
1.1
0.8
40
2000
1200
+6
-8
2.0
3.0
2.0
3.0
0.8
0.1
10
0.40
mA
µA
V
V
V
V
V
mA
mA
mA
mA
pF
kHz
5
pA
pA
µV/°C
ppm/°C
V
-2V ≤ V
IN
≤ +2V
.01
-V
IN
= +V
IN
≈ +2V
en
I
ILK
V
IN
= 0V, Full Scale = 2.000V
V
IN
= 0V
V
IN
= 0V
T
A
= 25°C
0° ≤ T
A
≤ +70°C
0.5
15
1
1
(ext. ref. 0ppm/°C)
V
IN
= +2V
0° ≤ T
A
≤ +70°C
0° ≤ T
A
≤ +70°C
0° ≤ T
A
≤ +70°C
0° ≤ T
A
≤ +70°C
0° ≤ T
A
≤ +70°C
0° ≤ T
A
≤ +70°C
DIGITAL
Note 1:
Tested in 4
1
/
2
digit (20,000 count) circuit shown in Figure 1, clock frequency 120kHz.
Note 2:
Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.
Note 3:
The Temperature range can be extended to +70°C and beyond as long as the auto-zero and reference capacitors are
increased to absorb the higher leakage of the ICL7135.
Note 4:
This specification relates to the clock frequency range over which the ICL7135 will correctly perform its various functions.
See “Clock Frequency” below for limitations on the clock frequency range in a system.
Note 5:
+5V Supply current for f
c
≠ 0 is I+ = I+ (f
c
= 0) + C
PD
x 5V x f
c
.
Note 6:
All pins are designed to withstand electrostatic discharge (ESD) levels in excess of 2000V. (Test circuit per MIL Std 883,
Method 3015.1)
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Maxim Integrated
│
3
ICL7135
4
1
/
2
Digit A/D Converter with
Multiplexed BCD Outputs
-5V
1 V-
UNDERRANGE 28
OVERRANGE 27
STROBE
26
RUN/HOLD 25
DIGITAL GND 24
OV
CLOCK
IN
120kHz
SET V
REF
= 1.000V
V
REF
IN
100kΩ
ANALOG
GND
100kΩ
27Ω
0.47µF
1.0µF
100kΩ
SIGNAL
INPUT
100kΩ
0.1µF
+5V
1µF
2 REFERENCE
3 ANALOG COMMON
4 INT. OUT
5 A-Z IN
6 BUFF OUT
7 REF. CAP-
8 REF. CAP+
9 IN LO
10 IN HI
11 V+
12 MSD D5
13 LSB B1
14 B2
integrator capacitor at the end of signal integrate is directly
proportional to the differential voltage between Input High
and Input Low, and is also directly proportional to the
length of the signal integrate phase. The signal integrate
phase lasts precisely 10,000 clock cycles. At the end of
this phase the input signal polarity is determined.
De-Integrate Phase
ICL7135
POLARITY 23
CLOCK IN 22
BUSY 21
LSD D1 20
D2 19
D3 18
D4 17
MSB B8 16
B4 15
Figure 1. ICL7135 Test Circuit
Detailed
Description
General Operation
The ICL7135 is divided into an Analog section and a
Digital section. The digital section includes the counters,
input and output interfaces, and control logic which controls
the timing of each measurement cycle. Each measurement
is divided into four phases: 1) auto-zero (AZ), 2) signal
integrate (INT), 3) reference deintegrate (DE), and 4) zero
integrator (ZI). The digital section controls the operation
of the analog section during each of these phases, using
counters and the state of the comparator to determine
when to start each of the four phases.
At the end of signal integrate, Input High and Input Low
are disconnected from the external pins. The integrator
non-inverting input pin is then internally connected to
Analog Common and the buffer input is connected to
one side of the reference capacitor. The other side of
the reference capacitor is connected to Analog Common.
The polarity at the output of the integrator (as detected
by the comparator at the end of signal integrate phase)
determines which terminal of the reference capacitor is
connected to the buffer input. The reference capacitor
polarity is chosen so that the integrator output will always
return towards Analog Common. Since the reference
capacitor was charged to the reference voltage during
the auto-zero phase, the integrator input voltage is now
the reference voltage. The De-Integrate phase lasts for
20,001 counts, or until the comparator detects that the
integrator output has crossed zero, whichever occurs first.
The time required to return to zero is proportional to the
input signal and is inversely proportional to the reference
voltage. The number of clock cycles required to return to
zero is counted by the digital section and is latched as the
measurement result.
V
IN
Displayed reading = 10,000 x
V
REF
Auto-Zero Phase
During auto-zero Input HI and Input LO are disconnected
from the input pins and are internally shorted to Analog
COMMON. The output of the comparator is connected
to the inverting input of the Integrator, and at the same
time the non-inverting input of the integrator is connected
to the input of the buffer. This feedback loop charges the
autozero capacitor, C
AZ
, to compensate for the offset
voltages of the buffer amplifier, integrator, and comparator.
Also during auto-zero,the reference capacitor is
connected to the voltage reference and is charged to the
reference voltage. The auto-zero cycle is a minimum of
9800 clock cycles, except after an over-range reading.
After an over-range, the extended zero integrate phase
reduces the auto-zero phase to 3800 clock cycles.
Zero Integrator Phase
Signal Integrate Phase
At the end of the auto-zero phase the auto-zero loop is
opened, and the Input High and Input Low are switched
to the external pins IN-HI and IN-LO. The analog section
integrates the differential voltage between Input High
and Input Low. The differential voltage must be within
the ICL7135’s common mode range. The voltage on the
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The last of the four phases is the zero integrator phase.
The non-inverting input of the integrator is internally shorted
to Analog Common and the buffer input is internally
connected to the output of the comparator. This closes
a loop that forces the integrator output to zero. Normally
this phase lasts only 100 to 200 counts, sufficient time
to remove the small residual charge on the integrator
capacitor caused by the comparator delay and the one
count delay created by sampling the comparator output
only once per clock cycle. However, an overrange condition
will exist when the integrator output does not return to
zero by the end of the De-Integrate phase, and can leave
a residual voltage on the integrator capacitor. In this case,
the Zero Integrator phase is increased to 6200 counts to
ensure that the integrator capacitor is fully discharged
before the next measurement cycle is started.
Analog Section
Analog COMMON
Analog COMMON is the Analog ground reference for the
ICL7135. If Input Low is at a voltage other than Analog
Maxim Integrated
│
4
ICL7135
4
1
/
2
Digit A/D Converter with
Multiplexed BCD Outputs
C
REF
C
REF
+
8
REF HI
2
C
REF
7
R
INT
BUFFER
6
V+
11
C
AZ
AUTO
ZERO
5
C
INT
INT
4
INTEGRATOR
A/Z
IN HI
10
INT
AZ
ANALOG
COMMON
IN LO
3
9
INT
DE(+)
DE(-)
A/Z + DE(±) + ZI
DE(-)
DE(+)
INPUT
HIGH
A/Z
COMPARATOR
A/Z
ZI
INPUT
LOW
ICL7135
1
V-
Figure 2. Analog Section of ICL7135
COMMON a common mode voltage will be introduced
and, although the ICL7135 has an excellent CMRR, Input
Low and Analog COMMON should be connected together
whenever possible. Analog COMMON is also the reference
point for the reference voltage. The Analog Common voltage is
normally connected to the system ground when using ±5V
supplies. When the ICL7135 is operated from a single
supply voltage the Analog Common should be connected
to a voltage source approximately halfway between V+
and ground.
Comparator
Input Buffer
The comparator monitors the voltage on the integrator
capacitor during deintegrate. The digital section samples
the comparator output once per clock cycle and terminates
the deintegrate cycle when the comparator changes its
state as the integrator voltage passes through zero. The
offset voltage of the comparator is not critical since the
auto-zero phase compensates for the offset. The output of
the comparator is the only output from the analog section
to the digital section.
The ICL7135 input buffer is a CMOS buffer with a common
mode input voltage range of approximately V+ -1.0V to
V- +1.5V. The quiescent current is approximately 100µA
and the buffer can deliver up to 40µ of output current with
excellent linearity.
Digital Section
Integrator
The integrator amplifier, similar to the buffer amplifier, can
deliver 20µA of output current with high linearity while
swinging to within 0.3V of either supply rail. The integrator’s
non-inverting terminal is connected to IN LO during the
signal integrate phase, so the voltage on the IN LO
terminal sets the starting point for the integrator output
during signal integrate. If IN LO is at a voltage other than
ground, this will limit the maximum allowable swing at the
integrator output, and the value of the integrating capaci-
tor should be increased. (Refer to
Component Selection)
As shown in Figure 3, the digital section consists of coun-
ters, latches, output multiplexer, and control logic. The
control logic monitors the counters and the comparator
to determine the start of each phase, and sends control
signals to the analog section to drive the analog switches
to the proper state for each measurement phase. The
control section also responds to the external input, RUN/
HOLD,
and creates the control outputs; OVERRANGE,
UNDERRANGE, BUSY, and
STROBE.
RUN/HOLD
When RUN/HOLD is high or open the ICL7135 will
continuously perform conversions with each measure-
ment being 40,002 clock cycles long. When RUN/HOLD
goes low, the ICL7135 will complete the measurement in
progress then remain in the auto-zero cycle, holding the
last reading. If RUN/HOLD goes high after the maximum
period assigned to deintegrate, a new conversion will
start, with a delay of 1 to 10,001 clock cycles between
