DATASHEET
LOW EMI CLOCK GENERATOR
Description
The ICS4231-03 generates a low EMI output clock
from a clock or crystal input. The device uses ICS’
proprietary mix of analog and digital Phase Locked
Loop (PLL) technology to spread the frequency
spectrum of the output, thereby reducing the frequency
amplitude peaks by several dB.
The ICS4231-03 offers four different center and down
spread selections. Refer to the MK1714-01/02 for the
widest selection of input frequencies and multipliers.
ICS offers a complete line of EMI reducing clock
generators. Consult us when you need to remove
crystals and oscillators from your board.
ICS4231-03
Features
•
•
•
•
Pin and function compatible to Cypress W42C31-03
Packaged in 8-pin SOIC (Pb free available)
Provides a spread spectrum output clock
Accepts a clock or crystal input and provides same
frequency dithered output
•
Input clock frequency of 10 to 33 MHz
•
Peak reduction by 8dB - 14dB typical on 3rd - 19th
odd harmonics
•
Spread percentage selections of
±
1.875%,
±
1.0%,
and -2.0%
•
Operating voltage of 5V
•
Advanced, low-power CMOS process
Block Diagram
VDD
FS1:0
OE#
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
CLK
X1/CLKIN
X2
Clock Buffer/
Crystal
Oscillator
GND
IDT™ / ICS™
LOW EMI CLOCK GENERATOR
1
ICS4231-03
REV A 110404
ICS4231-03
LOW EMI CLOCK GENERATOR
SSCG
Pin Assignment
X1/CLKIN
X2
GND
FS0
1
2
3
4
8
7
6
5
OE#
FS1
VDD
CLKOUT
Output Enable Function Table
OE#
(Pin 8)
0
1
Output Status
Running
Tri-state
8 pin (150 mil) SOIC
0 = connect to GND
1 = connect directly to VDD
Note: OE# pin has an internal pull-down resistor
Frequency Range and Spread Table
FS1
(Pin 7)
FS0
(Pin 4)
Clock Input
Frequency
(MHz)
10-20
10-20
20-33
20-33
Crystal Input
Frequency
(MHz)
10-20
10-20
20-25
20-25
Spread Amount
0
0
1
1
0
1
0
1
±
1.875%
±
1.0%
±
1.875%
-2.0%
Note: FS1:0 have internal pull-up resistors
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
X1/CLKIN
X2
GND
FS0
CLKOUT
VDD
FS1
OE#
Input
Output
Power
Input
Output
Power
Input
Input
Crystal or Clock Input.
Crystal output. Float for a clock input.
Connect to ground.
Select pin for input frequency and spread amount. See table above. Internal
pull up resistor.
Spread spectrum clock output per table above.
Connect to 5V.
Select pin for input frequency and spread amount. See table above. Internal
pull up resistor.
Output Enable. Active Low. See table above. Internal pull-down resistor.
IDT™ / ICS™
LOW EMI CLOCK GENERATOR
2
ICS4231-03
REV A 110404
ICS4231-03
LOW EMI CLOCK GENERATOR
SSCG
External Components
The ICS4231-03 requires a minimum number of
external components for proper operation.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the VDD
pin as possible. No vias should be used between the
decoupling capacitor and VDD pin. The PCB trace to
VDD pin should be kept as short as possible, as should
the PCB trace to the ground via.
2) To minimize EMI the 33Ω series termination resistor,
if needed, should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS4231-03. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 6 and 3, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50Ω trace (a commonly used trace
impedance) place a 33Ω resistor in series with the clock
line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20Ω
.
value of these capacitors is given by the following
equation:
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS4231-03. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5V to VDD+0.5V
0 to +70° C
-65 to +150° C
125° C
260° C
IDT™ / ICS™
LOW EMI CLOCK GENERATOR
3
ICS4231-03
REV A 110404
ICS4231-03
LOW EMI CLOCK GENERATOR
SSCG
DC Electrical Characteristics
Unless stated otherwise, VDD = 5V,
±
10%, Ambient Temperature 0 to +70° C
Parameter
Operating Voltage
Supply Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
Load Capacitance
Output Impedance
Input Pull-Up Resistor
Power-Up Time
Symbol
VDD
IDD
V
IH
V
IL
V
OH
V
OL
C
IN
Conditions
No load, at 3.3V
Min.
4.5
0.7VDD
Typ.
5
18
Max.
5.5
32
0.15VDD
Units
V
mA
V
V
V
V
pF
pF
Ω
KΩ
I
OH
= -24mA
I
OL
= 24mA
All pins except X1, X2
X1, X2, as seen by the
xtal, Note 1
2.5
0.4
5
17
20
500
7
Rout
First locked clock
cycle after Power
Good
5
ms
Note 1: Pins X1 and X2 each have 34 pF capacitance. When used with a crystal, the total combined
capacitance as seen by the crystal is 17 pF. If driving X1 with a clock input, the load capacitance will be
34 pF.
AC Electrical Characteristics
Unless stated otherwise, VDD =
5V±10%
, Ambient Temperature 0 to +70° C, C
L
=15pf
Parameter
Input Frequency
Output Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Output Rise Time
Output Fall Time
Jitter
Harmonic Reduction
Note 1: Measured with 15pF load
Symbol
Conditions
Input Clock
Time above VDD/2
Note 1
Min.
10
10
40
45
Typ.
Max. Units
33
33
60
MHz
MHz
%
%
ns
ns
ps
dB
50
2
2
55
5
5
300
t
OR
t
OF
0.8 to 2.4V, note 1
2.4 to 0.8V, note 1
cycle-to-cycle
8
IDT™ / ICS™
LOW EMI CLOCK GENERATOR
4
ICS4231-03
REV A 110404
ICS4231-03
LOW EMI CLOCK GENERATOR
SSCG
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
150
140
120
40
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
Marking Diagram
8
5
Marking Diagram (Pb free)
8
5
4231M-03
######
YYWW
1
4
1
4231M03L
######
YYWW
4
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “L” denotes Pb (lead) free package.
4. Bottom marking: country of origin.
IDT™ / ICS™
LOW EMI CLOCK GENERATOR
5
ICS4231-03
REV A 110404
