PRELIMINARY INFORMATION
ICS525-07/08
LVCMOS User Configurable Clock
Description
The ICS525-07/08 are the most flexible way to
generate a high-quality clock output from an
inexpensive crystal or clock input at low supply
voltages. The user can configure the device to produce
nearly any output frequency from any input frequency
by grounding or floating the select pins or by driving or
hard wiring the select pins high or low. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase-Locked
Loop (PLL) techniques, the device accepts a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 250 MHz. It can also produce a
highly accurate output clock from a given input clock,
keeping them frequency locked.
For similar capability with a serial interface, use the
ICS307.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew is not defined nor guaranteed.
Features
•
Packaged as 28-pin SSOP (150 mil body)
•
Available in Pb (lead) free package
•
User determines the output frequency by setting all
internal dividers
•
•
•
•
•
•
•
•
•
•
•
•
Eliminates need for custom oscillators
Low voltage operation
Pull-ups on all select inputs
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Compensated loop bandwidth
Enhanced low frequency operation (-08 version)
Low jitter
Duty cycle of 45/55 up to 200 MHz
Operating voltage of 1.8 V to 2.5 V
Ideal for oscillator replacement
Available in commercial and industrial temperature
ranges
Block Diagram
2
PD
X1/ICLK
Crystal
or clock
input
Crystal
Oscillator
X2
Reference
Divider
Phase
Comparator,
Charge
Pump,
and
Loop Filter
VCO
VCO
Divider
Divider
VDD
REF
VCO
Output
Divider
CLK
Optional crystal
capacitors
Optional crystal
capacitors
2
2
R
Configuration Pins
R
Configuration Pins
V Configuration Pins
V Configuration Pins
GND
GND
S Configuration Pins
S Configuration Pins
MDS 525-07/08 A
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS525-07/08
LVCMOS User Configurable Clock
Pin Assignment (ICS525-07)
R5
R6
S0
S1
S2
VDD
X1/ICLK
X2
GND
V0
V1
V2
V3
V4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
R3
R2
R1
R0
VDD
REF
CLK
GND
PD
V8
V7
V6
V5
Pin Descriptions (ICS525-07)
Pin
Number
1, 2,
24-28
3, 4, 5
6, 23
7
8
9, 20
10 - 18
19
21
22
Pin
Name
R5, R6,
R0-R4
S0, S1, S2
VDD
X1/ICLK
X2
GND
V0 - V8
PD
CLK
REF
Pin
Type
I(PU)
I(PU)
Power
X1
X2
Power
I(PU)
Input
Output
Output
Pin Description
Reference divider word input pins.
Select pins for output divider. See table on page 4.
Connect to VDD.
Crystal connection. Connect to a parallel resonant fundamental crystal or input clock.
Crystal connection. Connect to a crystal or leave unconnected for clock.
Connect to ground.
VCO divider word input pins.
Power-down. Active low. Turns off entire chip when low. Clock outputs stop low.
PLL output clock.
Reference output. Buffered crystal oscillator (or clock) output.
KEY: I(PU) = Input with internal pull-up resistor; X1, X2 = crystal connections
MDS 525-07/08 A
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS525-07/08
LVCMOS User Configurable Clock
Pin Assignment (ICS525-08)
R5
S3
S0
S1
S2
VDD
X1/ICLK
X2
GND
V0
V1
V2
V3
V4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
R3
R2
R1
R0
VDD
REF
CLK
GND
PD
V8
V7
V6
V5
Pin Descriptions (ICS525-08)
Pin
Number
1, 24-28
2, 3, 4, 5
6, 23
7
8
9, 20
10 - 18
19
21
22
Pin
Name
R5, R0-R4
S0, S1, S2,
S3
VDD
X1/ICLK
X2
GND
V0 - V8
PD
CLK
REF
Pin
Type
I(PU)
I(PU)
Power
X1
X2
Power
I(PU)
Input
Output
Output
Pin Description
Reference divider word input pins.
Select pins for output divider. See table on page 4.
Connect to VDD.
Crystal connection. Connect to a parallel resonant fundamental crystal or input clock.
Crystal connection. Connect to a crystal or leave unconnected for clock.
Connect to ground.
VCO divider word input pins.
Power-down. Active low. Turns off entire chip when low. Clock outputs stop low.
PLL output clock.
Reference output. Buffered crystal oscillator (or clock) output.
MDS 525-07/08 A
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS525-07/08
LVCMOS User Configurable Clock
Output Frequency and Output Divider Table (ICS525-07)
Output Frequency Range (MHz)
S2
S1
S0 CLK Output
Pin 5 Pin 4 Pin 3
Divider
Min
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
12
2
16
4
5
7
1
3
8.3
50
6.25
25
20
14.3
100
33.3
VDD = 2.5 V
Max
20.8
125
15.63
62.5
50
35.7
250
83.33
VDD = 1.8 V
Min
8.3
50
6.25
25
20
14.3
100
33.3
Max
20.8
125
15.63
62.5
50
35.7
250
83.33
Output Frequency and Output Divider Table (ICS525-08)
Output Frequency Range (MHz)
S3
S2
S1
S0 CLK Output
Pin 2 Pin 5 Pin 4 Pin 3
Divider
Min
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
7
8
9
10
11
13
14
15
17
19
48
128
23.9
15.9
11.9
9.5
6.8
6.0
5.3
4.8
4.3
3.7
3.4
3.2
2.8
2.5
1.0
0.4
VDD = 2.5 V
Max
200
200
200
158.4
113.1
99.0
88.0
79.2
72.0
60.9
56.6
52.8
46.6
41.7
16.5
6.2
VDD = 1.8 V
Min
23.9
15.9
11.9
9.5
6.8
6.0
5.3
4.8
4.3
3.7
3.4
3.2
2.8
2.5
1.0
0.4
Max
200
200
200
158.4
113.1
99.0
88.0
79.2
72.0
60.9
56.6
52.8
46.6
41.7
16.5
6.2
MDS 525-07/08 A
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
PRELIMINARY INFORMATION
ICS525-07/08
LVCMOS User Configurable Clock
External Components/Crystal
Selection
Decoupling Capacitors
The ICS525-07/08 require two 0.01µF decoupling
capacitors to be connected between VDD and GND,
one on each side of the chip. The capacitor must be
connected close to the device to minimize lead
inductance.
The phase detector must be kept in its operating range
according to this equation:
250kHz
<
f
IN
R
Optimum values for
V, R,
and
OD
are found iteratively
by applying the above equations. Choosing a smaller
value of
R
will give better jitter. A calculator program is
available on the ICS website to automate the process.
After determining
V, R,
and
OD,
convert them to the pin
address.
V8...0 = binary(V - 8)
Example: V = 17, V8...0 = 000001001
For the ICS525-07, R6...0 = binary(R - 2)
Example: R = 15, R6...0 = 0001101
For the ICS525-08, R5...0 - binary(R - 2)
Example: R = 15, R5...0 = 001101
S2...0 or S3...0 is configured according to the tables on
page 4.
All of the configuration pins have on-chip pull-up
resistors, so pins can be floated to generate a “1”, or
tied to ground for a “0”. They can also be driven directly
by logic signals.
Crystal Load Capacitors
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on
either).
Configuring the Frequency
The ICS525-07/08 output frequency is determined by
its internal dividers according to this equation:
f
OUT
=
V
*
f
IN
R
*
OD
Output Termination
The output driver impedance is approximately 17
ohms. Use a 33 ohm series termination resistor on
each output to match a 50 ohm trace.
V
is the feedback divider and can be 8, 9, 10, 12...519
(not 11).
For the ICS525-07,
R
is the reference divider and can
be 2, 3, 4...129.
For the ICS525-08,
R
can be 1, 2...64.
For the ICS525-07,
OD
can be 1, 2, 3, 4, 5, 7, 12, or 16.
For the ICS525-08,
OD
can be 2, 3, 4, 5, 7, 8, 9, 10, 11,
13, 14, 15, 17, 19, 48, or 128.
The VCO must be kept in its operating range according
to this equation:
50MHz
<
V
*
f
IN
R
Reference Source
The initial accuracy and temperature stability of the
output frequency is determined by the reference
frequency source, the crystal, or the input clock. The
PLL will track the input frequency, so if the crystal is
running at +5 ppm the CLK frequency will also be +5
ppm. A low amplitude sinusoidal reference (such as the
1 V p-p signal from a TCXO) can be used by the AC
coupling it to the X1 pin with a 0.1 µF capacitor. The X1
pin is self-biasing.
<
400MHz
MDS 525-07/08 A
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 101105
tel (408) 297-1201
●
www.icst.com
