DATASHEET
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
Description
The ICS527-04 Clock Slicer is the most flexible way to
generate an output clock from an input clock with zero
skew. The user can easily configure the device to
produce nearly any output clock that is multiplied or
divided from the input clock. The part supports
non-integer multiplications and divisions. Using
Phase-Locked Loop (PLL) techniques, the device
accepts an input clock up to 200 MHz and produces an
output clock up to 160 MHz.
The ICS527-04 aligns rising edges on PECLIN with
FBPECL at a ratio determined by the reference and
feedback dividers.
For other PECL output clocks, see the ICS507-01,
ICS525-03, or the MK3707. For PECL in and CMOS
out, see the ICS527-02. For CMOS in and PECL out
with zero delay, use the ICS527-03.
ICS527-04
Features
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Packaged as 28-pin SSOP (150 mil body)
Synchronizes fractional clocks rising edges
CMOS in to PECL out
PECL in to PECL out
Pin selectable dividers
Zero input to output skew
User determines the output frequency - no software
needed
Slices frequency or period
Input clock frequency of 1.5 MHz - 200 MHz
Output clock frequencies up to 160 MHz
Very low jitter
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low power CMOS process
Block Diagram
R6:R0
7
PECLIN
PECLIN
Divide
by 2
1
0
Reference
Divider
Phase Comparator,
Charge Pump, and
Loop Filter
Divide
by 2
1
0
Feedback
Divider
2
VCO
Output
Divider
2
VDD
RES
560 ohm
VDD
VDD
68 ohm
PECLO
180 ohm
VDD
68 ohm
PECLO
180 ohm
7
F6:F0
GND
2
S1:S0
FBPECL
FBPECL
IRANGE
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
1
ICS527-04
REV F 051310
ICS527-04
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
PECL ZDB AND MULTIPLIER/DIVIDER
Pin Assignment
R5
R6
IR A N G E
S0
S1
VDD
FBPECL
FBPECL
GND
P E C L IN
P E C L IN
F0
F1
F2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
R3
R2
R1
R0
VDD
PECLO
PECLO
GND
RES
F6
F5
F4
F3
Output Frequency and Output
Divider Table
S1
Pin 5
0
0
1
1
S0
Pin 4
0
1
0
1
Output Frequency (MHz)
PECLO Output Pair
10 - 80
5 - 40
2.5 - 20
20 -160
IRANGE Setting Table
IRANGE
0
1
Criteria
if (FBPECL < 80 MHz) and (PECLIN < 80 MHz)
if (FBPECL > 80 MHz) or (PECLIN > 80 MHz)
28-pin (150 mil) SSOP
Pin Descriptions
Pin
Number
1-2
24 - 28
3
4-5
6, 23
7
8
9, 20
10
11
12 - 18
19
21
22
Pin
Name
R5, R6,
R0-R4
IRANGE
S0, S1
VDD
FBPECL
FBPECL
GND
PECLIN
PECLIN
F0-F6
RES
PECLO
PECLO
Pin
Type
Input
Input
Input
Power
Input
Input
Power
Input
Input
Input
BIAS
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
Set for proper frequency range of input clocks. See table above.
Select pins for output frequency range. See table above. Internal pull-up.
Connect to +3.3 V.
PECL feedback input to PLL.
PECL feedback input to PLL.
Connect to ground
PECL input clock.
Complementary PECL input clock.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
Resistor connection to VDD for setting level of PECL outputs.
Complementary PECL output.
PECL output. Rising edge aligns with PECLIN when connected directly to
FBPECL.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
2
ICS527-04
REV F 051310
ICS527-04
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
PECL ZDB AND MULTIPLIER/DIVIDER
External Components
Decoupling Capacitors
The ICS527-04 requires two 0.01µF decoupling
capacitors to be connected between VDD and GND,
one on each side of the chip. They must be connected
close to the device to minimize lead inductance. The
output levels can be adjusted for different output and
load impedances. Refer to application note MAN09 for
more information on the RES and resistor network
values for the output clocks.
set.
Determining ICS527-04 Divider Settings
The user has full control in setting the desired output
clock over the range shown in the table on page 2. The
user should connect the divider select input pins directly
to ground (or VDD, although this is not required
because of internal pull-ups) during Printed Circuit
Board layout, so that the ICS527-04 automatically
produces the correct clock when all components are
soldered. It is also possible to connect the inputs to
parallel I/O ports in order to switch frequencies. The
configuration inputs: IRANGE, S1, S0, R6...0, F6...0 are
compatible with CMOS or TTL levels.
The output of the ICS527-04 can be determined by the
following simple equation:
PECL Termination Networks
The PECLO to FBPECL and PECLO to FBPECL
connections should be made directly underneath the
device, unless feedback is being routed through other
devices. The resistor divider networks should be placed
as close to the outputs as possible.
Typical 50
Ω
termination is shown in the Block Diagram
on page 1. For other termination schemes, see
MAN09.pdf.
FDW + 2
-
FB Frequency
= Input Frequency
×
-----------------------
RDW + 2
Eliminating the Delay Through Buffers or
Other Components
More complicated feedback schemes can be used,
such as incorporating low skew, multiple output buffers
in the feedback path. An example of this is given later in
the datasheet. The fundamental property of the
ICS527-04 is that it aligns rising edges on CLKIN and
FBPECL at a ratio determined by the reference and
feedback dividers. This means that any delay in the
feedback path will cause the PECL output edge to lead
PECLIN by the delay amount. So, by taking the PECL
output from another device as the input to FBPECL, the
delay through the other device can be eliminated.
Where:
Reference Divider Word (RDW) = 0 to 127
Feedback Divider Word (FDW) = 0 to 127
FB Frequency is the same as the output
frequency
Additionally, the following operating ranges should be
observed:
Input Frequency
-
300kHz
<
------------------------------------------
RDW + 2
Setting the Clock Slicer
Use IRANGE to select the input frequency range. If
either the PECLIN or FBPECL pair frequencies are
greater than (or equal to) 80 MHz, connect IRANGE to
VDD, or let it float. If both frequencies are less than 80
MHz, connect IRANGE to ground.
Choose S1 and S0 from the table on page 2, depending
on the output frequency.
Finally, the divider settings should be selected.
Following is a description of how the dividers should be
S1 and S0 should be selected depending on the
output frequency. The table on page 2 gives the
ranges.
The dividers are expressed as integers. For example, if
a 50 MHz output on CLK1 is desired from a 40 MHz
input, the reference divider word (RDW) should be 2
and the feedback divider word (FDW) should be 3 which
gives the required 5/4 multiplication. If multiple choices
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
3
ICS527-04
REV F 051310
ICS527-04
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
PECL ZDB AND MULTIPLIER/DIVIDER
of dividers are available, then the lowest numbers
should be used. In this example, the output divide (OD)
should be selected to be 2. Then R6:R0 is 0000010,
F6:F0 is 0000011 and S1:S0 is 00.
If you need assistance determining the optimum divider
settings, please send an e-mail to ics-mk@icst.com
with the desired input clock and the desired output
frequency.
Typical Example
The following connection diagram shows the implementation of the example from the previous section.
This will generate a 50 MHz clock synchronously with a 40 MHz input. The layout diagram below will
produce the waveforms shown on the bottom of the example.
VDD
R5
R6
IRANGE
S0
0.01 F
R4
R3
R2
R1
R0
VDD
PECL
PECL
GND
RES
F6
F5
F4
F3
560
180
0.01 F
S1
VDD
FBPECL
FBPECL
GND
VDD
50 MHz
40 MHz
40 MHz
PECLIN
PECLIN
F0
F1
F2
PECL output resistor network (50 ohm) is not
shown, but is identical to PECL
40 MHz
(PECLIN shown)
50 MHz PECL
50 MHz PECL
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
4
ICS527-04
REV F 051310
ICS527-04
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
PECL ZDB AND MULTIPLIER/DIVIDER
Multiple Output Example
In this example, an input clock of 125 MHz is used. Four low skew copies of 50 MHz PECL are required
aligned to the 125 MHz input clock. The following solution uses the ICS554-01A, which is a 1 to 4 PECL
buffer with low pin to pin skew.
VDD
R5
R6
IRANGE
S0
0.01 F
R4
R3
R2
R1
R0
VDD
ICS527-04
0.01 F
RN
OE
NC
VDD
VDD
S1
VDD
FBPECL
Q0
ICS554-01A
Q3
RN
PECLO
PECLO
GND
RES
F6
F5
F4
F3
RN
RN
RN
0.01 F
RN
Q0
Q3
RN
0.01 F
50 MHz
FBPECL
GND
Q1
Q2
RN
125 MHz
125 MHz
PECLIN
PECLIN
F0
F1
F2
560
RN
Q1
Q2
RN
GND
IN
GND
IN
The layout design above produces the waveforms shown below.
125 MHz, PECLIN
50 MHz, PECLO
(Complementary outputs are not shown)
Using the equation for selecting dividers gives:
50 MHz = 125 MHz *
(FDW + 2)
(RDW + 2)
If FDW = 0, then RDW = 3. This gives the required divide-by-5 function. Setting pin IRANGE = 1 (by leaving
it unconnected and using the internal pull-up) allows a higher speed input clock like the 125 MHz. The
FBPECL pair pins are connected to the Q1 outputs (chosen arbitrarily) of the ICS554. This aligns all the
outputs of the ICS554 with the 125 MHz input since the ICS527-04 aligns rising edges on the PECLIN and
FBPECL pins.
In this example, the resistor network needed for each PECLO output is represented by the RN boxes.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
5
ICS527-04
REV F 051310
NXP MCU
