P R E L I M I N A R Y I N F O R M AT I O N
ICS650-44
Spread Spectrum Clock Synthesizer
Description
The ICS650-44 is a spread spectrum clock synthesizer
intended for video projector and digital TV applications.
It generates three copies of an EMI optimized 50 MHz
clock signal (EMI peak reduction of 7 to 14 dB on 3rd
through 19th harmonics) through the use of Spread
Spectrum techniques from a 25 MHz crystal or clock
input. The modulation rate is 50 kHz.
Features
•
•
•
•
•
•
•
•
•
Packaged in 16-pin TSSOP (173 mil)
Supply voltages: VDD = 3.3 V, VDDO = 2.5 V
Peak-to-peak jitter: ±125 ps typ
Output duty cycle 45/55% (worst case)
25 MHz crystal or reference clock input
Zero (0) ppm frequency error on all output clocks
Advanced, low-power CMOS process
Industrial temperature range (-40 to +85°C)
Available in Pb (lead) free package
Block Diagram
VDD
3
25 MHz crystal
or clock input
X1/CLKIN
Crystal
OSC
X2
External capacitors are
required with a crystal
input.
VDDO
50M
PLL with
Spread
Spectrum
Control
Logic
50M
FS3:0
50M
GND
2
PDTS
MDS 650-44 C
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 080305
tel (408) 297-1201
●
www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-44
Spread Spectrum Clock Synthesizer
Pin Assignment
X1/ CLKIN
FS0
FS1
50M
VDD
GND
FS3
50M
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
VDD
PDTS
FS2
VDD
GND
VDDO
50M
Spread Spectrum and Output
Configuration Table
FS3 FS2
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Spread Type
Center
Center
Center
Center
Center
Center
Center
Center
Down
Down
Down
Down
Down
Down
Down
Off
SS Out
±0.25
±0.50
±0.75
±1.00
±1.25
±1.50
±1.75
±2.00
-0.5
-0.75
-1.0
-1.25
-1.5
-1.75
-2.0
Off
16-pin ( 173 mil) TSSOP
MDS 650-44 C
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 080305
tel (408) 297-1201
●
www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-44
Spread Spectrum Clock Synthesizer
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
X1/CLKIN
FS0
FS1
50M
VDD
GND
FS3
50M
50M
VDDO
GND
VDD
FS2
PDTS
VDD
X2
Pin
Type
Input
Input
Input
Output
Power
Power
Input
Output
Output
Power
Power
Power
Input
Input
Power
Output
Pin Description
Crystal input. Connect this pin to a 25 MHz crystal or external input
clock.
Select pin 0. Internal pull-up resistor. See table on page 2.
Select pin 1. Internal pull-up resistor. See table on page 2.
Spread Spectrum output. Weak internal pull-down when tri-stated.
Connect to +3.3 V.
Connect to ground.
Select pin 3. Internal pull-up resistor. See table on page 2.
Spread Spectrum output. Weak internal pull-down when tri-stated.
Spread Spectrum output. Weak internal pull-down when tri-stated.
Connect to +2.5 V.
Connect to ground.
Connect to +3.3 V.
Select pin 2. Internal pull-up resistor. See table on page 2.
Powers down entire chip. Tri-states CLK outputs when low. Internal
pull-up.
Connect to +3.3 V.
Crystal Output. Connect this pin to a 25 MHz crystal. Do not connect if
clock input is used.
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS650-44 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
MDS 650-44 C
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 080305
tel (408) 297-1201
●
www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-44
Spread Spectrum Clock Synthesizer
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS650-44. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-44. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature (max. of 10 seconds)
5V
Rating
-0.5 V to VDD+0.5 V
-40 to +85°C
-65 to +150°C
125°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (VDD, with respect to GND)
Power Supply Voltage (VDDO)
Power Supply Ramp Time, Figure 4
Min.
-40
+3.135
+2.375
Typ.
–
+3.3
+2.5
Max.
+85
+3.465
+2.625
4
Units
°C
V
V
ms
MDS 650-44 C
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 080305
tel (408) 297-1201
●
www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-44
Spread Spectrum Clock Synthesizer
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±5%, VDDO = 2.5 V ±5%
, Ambient Temperature -40 to +85°C
Parameter
Symbol
IDD
Conditions
no load
PDTS = 0, no load
no load
Min.
Typ.
27
40
4
1
Max.
Units
mA
uA
mA
uA
V
Operating Supply Current
IDDO
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output
Impedance
Internal Pull-up Resistor
Input Leakage Current
Internal Pull-down
Resistor
Input Capacitance
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
I
OS
Z
O
R
PU
I
I
R
PD
C
IN
PDTS = 0, no load
FS3:0, PDTS
FS3:0, PDTS
X1/CLKIN
X1/CLKIN
I
OH
= -4 mA
I
OL
= 4 mA
1.8
0.7 x
VDD
2
0.8
V
V
0.3 x
VDD
0.6
±50
20
V
V
V
mA
Ω
kΩ
uA
kΩ
pF
FS3:0, PDTS
FS3:0, PDTS, VIN=VDD
CLK outputs
Inputs
360
1
900
4
MDS 650-44 C
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 080305
tel (408) 297-1201
●
www.icst.com
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