DATASHEET
NETWORKING CLOCK SOURCE
Description
The ICS650-07C is a low cost, low jitter, high performance
clock synthesizer for networking applications. Using analog
Phase-Locked Loop (PLL) techniques, the device accepts a
12.5 MHz or 25.00 MHz clock or fundamental mode crystal
input to produce multiple output clocks for networking chips,
PCI devices, SDRAM, and ASICs. The ICS650-07C outputs
all have 0 ppm synthesis error.
See the MK74CB214, ICS551, and ICS552-01 for non-PLL
buffer devices which produce multiple low-skew copies of
these output clocks.
See the ICS570, ICS9112-16/17/18 for zero delay buffers
that can synchronize outputs and other needed clocks.
ICS650-07C
Features
•
Packaged in 20-pin tiny SSOP (QSOP)
•
Pb (lead) free package
•
12.5 MHz or 25.00 MHz fundamental crystal or clock
input
•
•
•
•
•
•
Six output clocks with selectable frequencies
SDRAM frequencies of 67, 83, 100, and 133 MHz
Buffered crystal reference output
Zero ppm synthesis error in all clocks
Ideal for PMC-Sierra’s ATM switch chips
Full CMOS output swing with 25 mA output drive
capability at TTL levels
•
Advanced, low power, sub-micron CMOS process
•
3.0 V to 5.5 V operating voltage
Block Diagram
VDD
2
CLKA1
/2
ACS1, 0
BCS1, 0
CCS
12.5 MHz or 25.00 MHz
Crystal or Clock
X1/ICLK
X2
Clock
Buffer/
Crystal
Oscillator
2
Optional crystal capacitors are shown and
may be required for tuning of initial accuracy
GND
OE (all outputs)
2
2
Clock
Synthesis
and Control
Circuitry
CLKA2
CLKB1
/2
CLKB2
CLKC1
CLKC2
REFOUT
IDT™ / ICS™
NETWORKING CLOCK SOURCE
1
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
Pin Assignment
ACS0
X2
X1/ICLK
VDD
ACS1
GND
CLKC1
CLKC2
CLKB2
CLKB1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
BCS1
BCS0
REFOUT
CLKA1
VDD
OE
GND
CLKA2
DC
CCS
20 pin (150 mil) SSOP
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
ACS0
X2
X1/ICLK
VDD
ACS1
GND
CLKC1
CLKC2
CLKB2
CLKB1
CCS
DC
CLKA2
GND
OE
VDD
CLKA1
REFOUT
BCS0
BCS1
Pin Type
XO
XI
Power
Input
Power
Output
Output
Output
Output
—
Output
Power
Input
Power
Output
Output
Input
Description
Crystal connection. Connect to a crystal or leave unconnected for clock input.
Crystal connection. Connect to fundamental crystal or clock input.
Connect to 3.3 V or 5 V. Must be same value as other VDD.
A clock select 1. Selects outputs on CLKA1 and CLKA2. Internal pull-up
resistor. See table below.
Connect to ground.
Clock C output 1. Depends on setting of CCS per table below.
Clock C output 2. Depends on setting of CCS per table below. Same as CLKC1.
Clock B output 2. Depends on setting of BCS1, 0 per table below.
Clock B output 1. Depends on setting of BCS1, 0 per table below.
Don’t Connect. Do not connect anything to this pin.
Clock A output 2. Depends on setting of ACS1, 0 per table below.
Connect to ground.
Output enable. Tri-states all outputs when low. Internal pull-up resistor.
Connect to VDD. Must be same value as other VDD.
Clock A output 1. Depends on setting of ACS1, 0 per table below.
Buffered reference clock output. Same frequency as crystal or clock input.
B clock select 1. Selects outputs on CLKB1 and CLKB2. See table below.
Tri-level Input A clock select 0. Selects outputs on CLKA1 and CLKA2. See table below.
Tri-level Input Clock C Select pin. Selects outputs on CLKC1 and CLKC2 per table below.
Tri-level Input B clock select 0. Selects outputs on CLKB1 and CLKB2. See table below.
IDT™ / ICS™
NETWORKING CLOCK SOURCE
2
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
For a 25 MHz Fundamental Crystal or Clock Input, use the following tables:
A Clocks Select Table (MHz)
ACS1
0
0
0
1
1
1
ACS0
0
M
1
0
M
1
CLKA1
100
TEST
75
33.3333
TEST
66.6667
CLKA2
OFF (low)
TEST
OFF (low)
16.6667
TEST
33.3333
B Clocks Select Table (MHz)
BCS1
0
0
0
1
1
1
BCS0
0
M
1
0
M
1
CLKB1
TEST
66.6667
100
83.3333
TEST
133.3333
CLKB2
TEST
33.3333
50
41.6667
TEST
66.6667
C Clocks Select Table (MHz)
CCS
0
M
1
CLKC1
125
TEST
75
CLKC2
125
TEST
75
REFOUT
= 25 MHz
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (automatically self biases to VDD/2)
IDT™ / ICS™
NETWORKING CLOCK SOURCE
3
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
For a 12.5 MHz Crystal or Clock Input, use the following tables:
A Clocks Select Table (MHz)
ACS1
0
0
0
1
1
1
ACS0
0
M
1
0
M
1
CLKA1
50
TEST
37.5
16.6667
TEST
33.3333
CLKA2
OFF (low)
TEST
OFF (low)
8.3333
TEST
16.6667
B Clocks Select Table (MHz)
BCS1
0
0
0
1
1
1
BCS0
0
M
1
0
M
1
CLKB1
TEST
33.3333
50
41.66667
TEST
66.6667
CLKB2
TEST
16.6667
25
20.8333
TEST
33.3333
C Clocks Select Table (MHz)
CCS
0
M
1
CLKC1
62.5
TEST
37.5
CLKC2
62.5
TEST
37.5
REFOUT
= 12.5 MHz
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (automatically self biases to VDD/2)
IDT™ / ICS™
NETWORKING CLOCK SOURCE
4
ICS650-07C
REV D 102709
ICS650-07C
NETWORKING CLOCK SOURCE
CLOCK SYNTHESIZER
External Components
The ICS650-07C requires a minimum number of external
components for proper operation.
impedance) place a 33Ω resistor in series with the clock line,
as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω
.
Crystal Information
Decoupling Capacitor
Decoupling capacitors of 0.01µF must be connected
between each VDD and GND (pins 4 and 6, pins 16 and 14),
as close to the device as possible. For optimum device
performance, the decoupling capacitor should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
The crystal used should be a fundamental mode (do not use
third overtone), parallel resonant. Crystal capacitors should
be connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value of these capacitors
is given by the following equation:
Crystal caps (pF) = (C
L
- 6) x 2
In the equation, C
L
is the crystal load capacitance. So, for a
crystal with a 16 pF load capacitance, two 20 pF capacitors
should be used. If a clock input is used, drive it into X1 and
leave X2 unconnected.
Series Termination Resistor
When the PCB trace between the clock outputs and the
loads are over 1 inch, series termination should be used. To
series terminate a 50Ω trace (a commonly used trace
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-07C. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature (20 seconds max)
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
-40 to +85° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured with respect to GND)
Min.
0
-40
+3.0
Typ.
Max.
+70
+85
Units
°
C
°
C
V
+3.3
+5.5
IDT™ / ICS™
NETWORKING CLOCK SOURCE
5
ICS650-07C
REV D 102709
