ICS650-11C
Alcatel Clock Source
Description
The ICS650-11C is a low-cost, low-jitter,
high-performance clock synthesizer optimized for
Alcatel system requirements. Using analog/digital
Phase-Locked Loop (PLL) techniques, the device
accepts a parallel resonant 17.664 MHz crystal input to
produce up to five output clocks.
Features
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Packaged in 20-pin tiny SSOP (QSOP), Pb-free
Operating VDD of 3.3 V
Inexpensive 17.664 MHz crystal or clock input
Provides selectable 80 MHz or 78.9 MHz clock
Provides selectable 59.23 MHz clock
Provides selectable 25 MHz or 33 MHz clock
Provides selectable 70.6 MHz or 50.78 MHz clock
Provides fixed 17.664 MHz clock
Duty cycle of 40/60
Advanced, low-power CMOS process
Industrial temperature range
Block Diagram
VDD
GND
SEL-P
SB0:1
SC0:1
Clock
Synthesis
Circuitry
25 MHz or 33 MHz
59.23 MHz
80 MHz or 78.9 MHz
70.6 MHz or 50.78 MHz
17.664 MHz
crystal
X1
Crystal
Oscillator
X2
17.664 MHz
MDS 650-11C
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Rev J 051310
tel (408) 297-1201
●
www.icst.com
ICS650-11C
Alcatel Clock Source
Pin Assignment
SB0
X2
X1
VDD
SB1
GND
59.23M
80M/78.9M
DC
70.6M/50.78M
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
SEL-P
DC
DC
VDD
SC0
GND
17.664M
25/33M
SC1
Processor Clock (MHz)
SEL-P
0
1
Pin 12
33.0
25.0
0 = connect directly to ground
1 = connect directly to VDD
SC Clock (MHz)
SC1
0
0
1
SC0
0
1
0
Pin 10
OFF
70.656
50.784
20-pin (150 mil) SSOP
SB Clock (MHz)
SB1
0
1
SB0
0
1
Pin 7
Low
59.23
Pin 8
80
78.9
Pin Descriptions
Pin
Number
1
2
3
4, 16
5
6, 14, 20
7
8
9, 17, 18
10
11
12
13
15
19
Pin
Name
SB0
X2
X1
VDD
SB1
GND
59.32M
80M/78.9M
DC
SC1
25/33M
17.664M
SC0
SEL-P
Pin
Type
Input
XO
XI
Input
Input pin. See table above.
Pin Description
Crystal connection. Connect to a parallel mode 17.664 MHz crystal. Leave
open for clock.
Crystal connection. Connect to a parallel mode 17.664 MHz crystal or clock.
Select pin. See table above.
Power Connect to VDD. Must be same value as other VDD’s. Decouple with pin 6.
Power Connect to ground.
Output B1 clock. See table above.
Output B2 clock. See table above.
—
Input
Don’t connect. Do not connect this pin to anything.
Select pin. See table above.
70.6M/50.78M Output SC clock. See table above.
Output 25 MHz or 33 MHz clock output. Determined by SEL-P per table above.
Output 17.664 MHz buffered reference clock output.
Input
Input
Select pin. See table above.
Select pin. Determines frequency of pin 12 per table above.
MDS 650-11C
Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Rev J 051310
www.icst.com
ICS650-11C
Alcatel Clock Source
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS650-11C must be isolated from system power
supply noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS650-11C. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal
(C
L
-6 pF)*2. In this equation, C
L
= crystal load
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2 = 20].
MDS 650-11C
Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Rev J 051310
www.icst.com
ICS650-11C
Alcatel Clock Source
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-11C. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
Conditions
Referenced to GND
Referenced to GND
7V
Rating
-0.5 V to VDD+0.5 V
-40 to +85° C
-65 to +150° C
Max. of 10 seconds
260° C
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V,
Ambient Temperature -40 to +85° C
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Operating Supply Current
Short Circuit Current
Input Capacitance
Notes:
Symbol
VDD
V
IH
V
IL
V
OH
V
OL
V
OH
I
DD
I
OS
Conditions
SEL input
SEL input
I
OH
= -8 mA
I
OL
= 8 mA
I
OH
= -8 mA
No Load, Note 1
Each output
Except X1, X2
Min.
3.0
VDD-0.5
Typ.
3.3
Max.
3.6
0.5
Units
V
V
V
V
V
V
mA
mA
pF
2.4
0.4
VDD-0.4
25
±50
7
1. With all clocks at highest frequencies.
MDS 650-11C
Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Rev J 051310
www.icst.com
ICS650-11C
Alcatel Clock Source
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V,
Ambient Temperature -40 to +85° C
Parameter
Input Crystal or Clock Frequency
Output Clocks Accuracy (synthesis error)
Symbol
Conditions
25 MHz
33 MHz
80 MHz
Min.
Typ.
17.664
0
Max. Units
MHz
-0.05
0.04
-0.04
1.5
1.5
%
%
%
ns
ns
%
%
ps
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Cycle-to-cycle Jitter
t
OR
t
OF
0.8 to 2.0 V
2.0 to 0.8 V
80 MHz, at VDD/2
Other clocks, at VDD/2
25/33 MHz, 80 MHz
40
45
50
50
295
60
55
MDS 650-11C
Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Rev J 051310
www.icst.com
