DATASHEET
DIGITAL VIDEO CLOCK SOURCE
Description
The ICS660 provides clock generation and conversion for
clock rates commonly needed in digital video equipment,
including rates for MPEG, NTSC, PAL, and HDTV. The
ICS660 uses the latest PLL technology to provide excellent
phase noise and long term jitter performance for superior
synchronization and S/N ratio.
For audio sampling clocks generated from 27 MHz, use the
ICS661.
Please contact IDT if you have a requirement for an input
and output frequency not included here - we can rapidly
modify this product to meet special requirements.
ICS660
Features
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Packaged in 16-pin TSSOP
Pb-free packaging, RoHS compliant
Clock or crystal input
Low phase noise
Low jitter
Exact (0 ppm) multiplication ratios
Power-down control
Reference clock output available
Block Diagram
VDD (P2)
VDD (P3)
VDDO
VDDR
X2
Crystal
Oscillator
REF
X1/REFIN
SELIN
S3:0
PLL Clock
Synthesis
4
CLK
GND (P13)
GND (P6)
GND (P5)
IDT™ / ICS™
DIGITAL VIDEO CLOCK SOURCE
1
ICS660
REV G 051310
ICS660
DIGITAL VIDEO CLOCK SOURCE
CLOCK SYNTHESIZER
Pin Assignment
X1/REFIN
VDD
VDD
S0
GND
GND
S3
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
REF
VDDR
GND
SELIN
VDDO
S1
CLK
Output Clock Selection Table
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input
Frequency
(MHz)
13.5
13.5
27
27
Pass thru
74.25
74.175824
16.9344
125
14.3181818
106.25
27.027
27
27
27
Output
Frequency
(MHz)
74.25
74.175824
74.25
74.175824
Input Freq
74.175824
74.25
27
106.25
27
125
27
27.027
14.3181818
17.73447205
1
Power down
16-pin 4.40 mil body, 0.65 mm pitch TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
-
0.16 ppm compared to PAL specification
Pin
Name
X1/REFIN
VDD
VDD
S0
GND
GND
S3
S2
CLK
S1
VDDO
SEL
GND
VDDR
REF
X2
Pin
Type
Input
Power
Power
Input
Power
Power
Input
Input
Output
Input
Power
Input
Power
Power
Output
Input
Power supply for crystal oscillator.
Power supply for PLL.
Pin Description
Connect this pin to a crystal or clock input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Ground for output stage.
Ground for PLL.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Clock output.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Power supply for output stage.
Low for clock input, high for crystal. On chip pull-up.
Connect to ground.
Power supply for reference output. Ground to turn off REF.
Reference clock output.
Connect this pin to a crystal. Leave open if using a clock input.
IDT™ / ICS™
DIGITAL VIDEO CLOCK SOURCE
2
ICS660
REV G 051310
ICS660
DIGITAL VIDEO CLOCK SOURCE
CLOCK SYNTHESIZER
Application Information
Series Termination Resistor
Clock output traces should use series termination. To series
terminate a 50Ω trace (a commonly used trace impedance),
place a 33Ω resistor in series with the clock line, as close to
the clock output pin as possible. The nominal impedance of
the clock output is 20Ω
.
capacitance of the board to match the nominally required
crystal load capacitance. To reduce possible noise pickup,
use very short PCB traces (and no vias) been the crystal
and device.
The value of the load capacitors can be roughly determined
by the formula C = 2(C
L
- 6) where C is the load capacitor
connected to X1 and X2, and C
L
is the specified value of the
load capacitance for the crystal. A typical crystal C
L
is 18 pF,
so C = 2(18 - 6) = 24 pF. Because these capacitors adjust
the stray capacitance of the PCB, check the output
frequency using your final layout to see if the value of C
should be changed.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS660
must be isolated from system power supply noise to perform
optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the ICS660
should use one common connection to the PCB power
plane as shown in the diagram on the next page. The ferrite
bead and bulk capacitor help reduce lower frequency noise
in the supply that can lead to output clock phase modulation.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1) Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted next to the device
with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, and obtain the best signal integrity, the
33Ω series termination resistor should be placed close to
the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the ICS660. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
Recommended Power Supply Connection for
Optimal Device Performance
V D D P in
C onnection to 3.3V
P ow er P lane
Ferrite
Bead
V D D P in
B ulk D ecoupling C apacitor
(such as 1 F Tantalum )
V D D P in
0.01
F D ecoupling C apacitors
All power supply pins must be connected to the same
voltage, except VDDR and VDDO, which may be connected
to a lower voltage in order to change the output level. If the
reference output is not used, ground VDDR.
Crystal Load Capacitors
If a crystal is used, the device crystal connections should
include pads for capacitors from X1 to ground and from X2
to ground. These capacitors are used to adjust the stray
IDT™ / ICS™
DIGITAL VIDEO CLOCK SOURCE
3
ICS660
REV G 051310
ICS660
DIGITAL VIDEO CLOCK SOURCE
CLOCK SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS660. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
5.5 V
Rating
-0.5 V to VDD+0.5 V
-40 to +85° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.0
Typ.
Max.
+85
+3.6
Units
°
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±10%,
Ambient Temperature -40 to +85° C
Parameter
Operating Voltage
Symbol
VDD
VDDO
VDDR
IDD
IDDPD
V
IH
V
IL
V
OH
V
OH
V
OL
I
OS
Z
OUT
C
IN
R
PU
Conditions
Min.
3.0
2.5
2.5
Typ.
Max.
3.6
VDD
VDD
Units
V
V
V
mA
µA
V
Supply Current
Standby Supply Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output Impedance
Input Capacitance
Internal Pull-up Resistor
No Load
2
25
75
0.8
V
V
V
I
OH
= -4 mA
I
OH
= -20 mA
I
OL
= 20 mA
Each output
input pins
VDD-0.4
2.4
0.4
±65
20
7
120
V
mA
Ω
pF
kΩ
IDT™ / ICS™
DIGITAL VIDEO CLOCK SOURCE
4
ICS660
REV G 051310
ICS660
DIGITAL VIDEO CLOCK SOURCE
CLOCK SYNTHESIZER
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±10%,
Ambient Temperature -40 to +85° C
Parameter
Crystal Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Duty Cycle
Power up time
Power down time
Jitter, short term
Jitter, short term
Jitter, long term
Jitter, long term
Single sideband phase noise
Single sideband phase noise
Actual mean frequency error
versus target
Symbol
t
OR
t
OF
t
OD
t
PU
t
PD
Conditions
20% to 80%, 15 pF load
80% to 20%, 15 pF load
at VDD/2, 15 pF load
inputs out of PD state to
clocks stable
inputs in PD state to
clocks off
Reference clock off
Reference clock on
Reference clock off; 10
us delay
Reference clock on; 10
us delay
Reference clock off; 10
kHz offset
Reference clock on; 10
kHz offset
Note 1
Min.
Typ.
Max.
28
1.5
1.5
Units
MHz
ns
ns
%
ms
µs
ps p-p
ps p-p
ps p-p
ps p-p
dBc
dBc
ppm
40
49 to 51
60
10
1
100
125
300
300
-110
-110
0
Note 1: Selection 1111 is 0.16 ppm lower than the PAL specified frequency
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
78
70
68
37
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
IDT™ / ICS™
DIGITAL VIDEO CLOCK SOURCE
5
ICS660
REV G 051310
