ICS664-04
PECL Digital Video Clock Source
Description
The ICS664-04 provides clock generation and
conversion for clock rates commonly needed in HDTV
digital video equipment. The ICS664-04 uses the latest
Phase-Locked Loop (PLL) technology to provide
excellent phase noise and long-term jitter performance
for superior synchronization and S/N ratio.
For audio sampling clocks generated from 27 MHz, use
the ICS661.
Please contact ICS if you have a requirement for an
input and output frequency not included in this
document. ICS can rapidly modify this product to meet
special requirements.
Features
•
•
•
•
•
•
•
•
•
Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Clock or crystal input
Low phase noise
Low jitter
Exact (0 ppm) multiplication ratios
Power-down control
Improved phase noise over ICS660
Differential outputs
Block Diagram
VDD (P2)
VDD (P3)
VDDO
VDD (P10)
X2
Crystal
Oscillator
X1/REFIN
SELIN
S3:0
4
PLL Clock
Synthesis
CLK
CLK
GND (P6)
GND (P5)
GND (P12)
MDS 664-04 A
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 040805
tel (408) 297-1201
●
www.icst.com
ICS664-04
PECL Digital Video Clock Source
Pin Assignment
X1/REFIN
VDD
VDD
S0
GND
GND
S3
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
VDDO
CLK
CLK
GND
SELIN
VDD
S1
Output Clock Selection Table
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Input
Frequency
(MHz)
Pass thru
27
27
13.5
13.5
27
27
74.25
74.175824
74.25
74.175824
54
54
54
27
Output
Frequency
(MHz)
Power down
Input Freq
74.25
74.175824
74.25
74.175824
148.5
148.351648
54
54
27
27
74.25
74.175824
13.5
13.5
16-pin 4.40 mil body, 0.65 mm pitch TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
X1/REFIN
VDD
VDD
S0
GND
GND
S3
S2
S1
VDD
SELIN
GND
CLK
CLK
VDDO
X2
Pin
Type
Input
Power
Power
Input
Power
Power
Input
Input
Input
Power
Input
Power
Output
Output
Power
Input
Power supply for crystal oscillator.
Power supply for PLL.
Pin Description
Connect this pin to a crystal or clock input
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Ground for PLL.
Ground for oscillator.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Output frequency selection. Determines output frequency per table above. On chip pull-up.
Power supply.
Low for clock input, high for crystal. On chip pull-up.
Ground for output stage
Complimentary clock output.
Clock output.
Power supply for output stage.
Connect this pin to a crystal. Leave open if using a clock input.
MDS 664-04 A
2
●
Revision 040805
tel (408) 297-1201
●
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
www.icst.com
ICS664-04
PECL Digital Video Clock Source
Application Information
Termination Resistor
Terminate the outputs with 50Ω to ground.
adjust the stray capacitance of the board to match the
nominally required crystal load capacitance. To reduce
possible noise pickup, use very short PCB traces (and
no vias) been the crystal and device.
The value of the load capacitors can be roughly
determined by the formula C = 2(C
L
- 6) where C is the
load capacitor connected to X1 and X2, and C
L
is the
specified value of the load capacitance for the crystal.
A typical crystal C
L
is 18 pF, so C = 2(18 - 6) = 24 pF.
Because these capacitors adjust the stray capacitance
of the PCB, check the output frequency using your final
layout to see if the value of C should be changed.
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS664-04 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the ICS664-04 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The external crystal should be mounted next to the
device with short traces. The X1 and X2 traces should
not be routed next to each other with minimum spaces,
instead they should be separated and away from other
traces.
3) To minimize EMI, and obtain the best signal integrity,
the 50Ω series termination resistor should be placed
close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the ICS664-04. This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Recommended Power Supply Connection for
Optimal Device Performance
V D D P in
C onnection to 3.3V
P ow er P lane
Ferrite
Bead
V D D P in
B ulk D ecoupling C apacitor
(such as 1 F Tantalum )
V D D P in
0.01
F D ecoupling C apacitors
All power supply pins must be connected to the same
voltage, except VDDO, which may be connected to a
lower voltage in order to change the output level.
To achieve the absolute minimum jitter, power the part
with a dedicated LDO regulator, which will provide high
isolation from power supply noise. Many companies
produce very small, inexpensive regulators; an
example is the National Semiconductor LP2985.
Crystal Load Capacitors
If a crystal is used, the device crystal connections
should include pads for capacitors from X1 to ground
and from X2 to ground. These capacitors are used to
MDS 664-04 A
3
●
Revision 040805
tel (408) 297-1201
●
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
www.icst.com
ICS664-04
PECL Digital Video Clock Source
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS664-04. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
5.5 V
Rating
-0.5V to VDD+0.5 V
0 to +70° C
-65 to +150° C
125° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.0
Typ.
Max.
+70
+3.6
Units
°C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±10%,
Ambient Temperature 0 to +70° C
Parameter
Operating Voltage
Supply Current
Standby Supply Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
Internal Pull-up Resistor
Symbol
VDD
VDDO
IDD
IDDPD
V
IH
V
IL
V
OH
V
OL
C
IN
R
PU
Conditions
Min.
3.0
2.5
Typ.
Max.
3.6
VDD
Units
V
V
mA
µA
V
No Load
2
25
75
0.8
VDDO-1.5
VDDO-2.0
VDDO-1.1
VDDO-1.8
7
120
V
V
V
pF
kΩ
Input pins
Input pins
MDS 664-04 A
4
●
Revision 040805
tel (408) 297-1201
●
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
www.icst.com
ICS664-04
PECL Digital Video Clock Source
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±10%,
Ambient Temperature 0 to +70° C
Parameter
Crystal Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Duty Cycle
Power-up Time
Power-down Time
Peak-to-peak Jitter, Short
term
Peak-to-peak Jitter, Long
term
Single Sideband Phase
Noise
Actual Mean Frequency
Error versus Target
Symbol
t
OR
t
OF
t
OD
t
PU
t
PD
Conditions
20% to 80%, C
L
=5 pF
80% to 20%, C
L
=5 pF
at VDD/2, C
L
=5 pF
Inputs out of PD state
to clocks stable
Inputs in PD state to
clocks off
Min.
Typ.
Max.
28
1.5
1.5
Units
MHz
ns
ns
%
ms
µs
ps
ps
dBc
ppm
40
49 to 51
60
10
1
70
10 µs delay
10 kHz offset
300
-120
0
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
78
70
68
37
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
Typical Output Termination
ICS664-04
CLK
50 Ohm
MDS 664-04 A
5
●
Revision 040805
tel (408) 297-1201
●
Integrated Circuit Systems, Inc.
●
525 Race Street, San Jose, CA 95126
www.icst.com
