DATASHEET
QUADRACLOCK QUADRATURE DELAY BUFFER
Description
The ICS672-01/02 are zero delay buffers that generate four
output clocks whose phases are spaced at 90° intervals.
Based on IDT’s proprietary low jitter Phase-Locked Loop
(PLL) techniques, each device provides five low-skew
outputs, with clock rates up to 84 MHz for the ICS672-01
and up to 135 MHz for the ICS672-02. By providing outputs
delayed one quarter clock cycle, the device is useful for
systems requiring early or late clocks. The ICS672-01/02
include multiplier selections of x0.5, x1, x2, x3, x4, x5, or x6.
They also offer a mode to power-down all internal circuitry
and tri-state the outputs. In normal operation, output clock
FBCLK is tied to the FBIN pin.
IDT manufactures the largest variety of clock generators
and buffers, and is the largest clock supplier in the world.
ICS672-01/02
Features
•
Packaged in 16-pin SOIC
•
Available in Pb (lead) free package
•
Input clock range from 5 MHz to 150 MHz (depends on
multiplier)
•
Clock outputs from up to 84 MHz (ICS672-01) and up to
135 MHz (ICS672-02)
•
Zero input-output delay
•
Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections
•
Four accurate (<250 ps) outputs with 0°, 90°, 180°, and
270° phase shift from ICLK, and one FBCLK (0°)
•
•
•
•
•
•
•
Separate supply for output clocks from 2.5 V to 5 V
Full CMOS outputs (TTL compatible)
Tri-state mode for board-level testing
Includes Power-down for power savings
Advanced, low power, sub-micron CMOS process
3.3 V to 5 V operating voltage
Industrial temperature version available
Block Diagram
VDD
GND
VDDIO
2
IN
PLL
Multiplier
and
Quadrature
Generation
3
CLK0
CLK90
CLK180
CLK270
CLKFB
FBIN
S2:S0
3
Control
Logic
Power Down plus Tri-state
External
Feedback
IDT™ / ICS™
QUADRACLOCK QUADRATURE DELAY BUFFER
1
ICS672-01/02
REV G 092506
ICS672-01/02
QUADRACLOCK QUADRATURE DELAY BUFFER
ZERO DELAY BUFFER
Pin Assignment
ICLK
CLK90
CLK180
CLK270
VDDIO
GND
GND
S0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBIN
FBCLK
CLK0
VDD
GND
VDD
S2
S1
Output Clock Mode Select Table
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Output Clocks
Power-down + tri-state
x1
x2
x3
x4
x5
x6
x0.5
Pin Descriptions
Pin
Number
1
2
3
4
5
6, 7, 12
8
9
10
11, 13
14
15
16
Pin
Name
ICLK
CLK90
CLK180
CLK270
VDDIO
GND
S0
S1
S2
VDD
CLK0
FBCLK
FBIN
Pin
Type
Input
Clock input.
Pin Description
Output Clock output (90° delayed from CLK0).
Output Clock output (180° delayed from CLK0).
Output
Power
Power
Input
Input
Input
Power
Clock output (270° delayed from CLK0).
Supply voltage for input and output clocks. Must not exceed VDD.
Connect to ground.
Select input 0. See table above.
Select input 1. See table above.
Select input 2. See table above.
Connect to 3.3 V or 5.0 V.
Output Clock output phase aligned to ICLK.
Output Feedback clock output (0° phase shift from CLK0).
Input
Feedback clock input. in normal operation, connect to FBCLK.
IDT™ / ICS™
QUADRACLOCK QUADRATURE DELAY BUFFER
2
ICS672-01/02
REV G 092506
ICS672-01/02
QUADRACLOCK QUADRATURE DELAY BUFFER
ZERO DELAY BUFFER
External Components
The ICS672-01/02 requires a minimum number of external components for proper operation. Decoupling capacitors
of 0.01µF should be connected between VDD and GND on pins 11 and 12, and VDD and GND on pins 13 and 12,
and VDDIO and GND on pins 5 and 6, as close to the device as possible. A series termination resistor of 33Ω may
be used close to each clock output pin to reduce reflections.
Operation and Applications
The ICS672-01/02 each provide a total of five output clocks with multiple phase shifts relative to the input clock
(ICLK). Phase shifts of 0° (CLK0), 90° (CLK90), 180° (CLK180), and 270° (CLK270) are provided, plus one
feedback clock (FBCLK). All output clocks will be a multiple of the input clock, as determined by the table on page
2. Refer to the illustrations in Figure 1 and Figure 2.
FBCLK is connected to the feedback input (FBIN) to provide a zero delay through the ICS672-01/02. FBCLK has a
0° phase shift from ICLK.
ICLK
CLK0,
FBCLK
CLK90
CLK180
CLK270
Figure 1. Phase alignment of input and output clocks (x1 multiplier)
ICLK
CLK0,
FBCLK
CLK90
CLK180
CLK270
Figure 2. Phase alignment of input and output clocks (x2 multiplier)
IDT™ / ICS™
QUADRACLOCK QUADRATURE DELAY BUFFER
3
ICS672-01/02
REV G 092506
ICS672-01/02
QUADRACLOCK QUADRATURE DELAY BUFFER
ZERO DELAY BUFFER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS672-01/02. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Electrostatic Discharge (MIL-STD-883)
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial, -02 only)
Storage Temperature
Junction Temperature
Soldering Temperature
-0.5 V to 7 V
Rating
-0.5 V to VDD+0.5 V
2000 V
0 to +70°C
-40 to +85°C
-65 to +150°C
150°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.13
Typ.
Max.
+70
+5.5
Units
°C
V
DC Electrical Characteristics
VDD = VDDIO = 3.3 V,
Ambient temperature 0 to +70°C, unless stated otherwise
Parameter
Operating Voltage
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage,
CMOS level
Operating Supply
Current
Symbol
VDD
VDDIO
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
Conditions
Min.
3.13
2.375
Typ.
Max.
5.50
VDD
VDDIO/2-0.5
Units
V
V
V
V
V
V
V
V
V
ICLK only
ICLK only
VDDIO/2+0.5
2
0.8
I
OH
= -12 mA
I
OL
= 12 mA
I
OH
= -8 mA
No Load, S1=1, S0=0,
S2=0, Note 1
2.4
0.4
VDDIO-0.4
11
mA
IDT™ / ICS™
QUADRACLOCK QUADRATURE DELAY BUFFER
4
ICS672-01/02
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ICS672-01/02
QUADRACLOCK QUADRATURE DELAY BUFFER
ZERO DELAY BUFFER
Parameter
Operating Supply
Current
Short Circuit Current
Input Capacitance
Symbol
IDD
I
OS
C
IN
Conditions
No Load, S1=1, S0=0,
S2=0, Note 2
Each output
OE, select pins
Min.
Typ.
22
±50
7
Max.
Units
mA
mA
pF
AC Electrical Characteristics
VDD = VDDIO = 3.3 V,
Ambient Temperature 0 to +70°C, unless stated otherwise
Parameter
Input Clock Frequency
Output Clock Frequency
Output Clock Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle,
VDDIO = 3.3 V
Phased Outputs
Accuracy
Input to Output Skew
Maximum Absolute Jitter
Cycle to Cycle Jitter
Symbol
f
IN
Note 3
Conditions
ICS672-01
ICS672-02
Min.
5
15
15
Typ.
Max. Units
150
84
135
1.0
1.0
MHz
MHz
MHz
ns
ns
%
ps
ps
ps
ps
t
OR
t
OF
t
DC
0.8 to 2.0 V, no load, C
L
= 15 pF
2.0 to 0.8 V, no load, C
L
= 15 pF
At VDDIO/2
Rising edges at VDDIO/2,
Note 4
ICLK to CLK0, Note 5
15 pF loads
45
-250
-300
75
150
50
55
250
300
Note 1: With ICLK = 20 MHz, FBCLK to FBIN, all outputs at 40 MHz.
Note 2: With ICLK = 66.5 MHz, FBCLK to FBIN, all outputs at 133 MHz.
Note 3: Value depends on multiplier. Must also meet output clock frequency.
Note 4: With CLK0CLK270 equally loaded, and output frequency > 60 MHz.
Note 5: Rising edge of ICLK compared with rising edge of CLk0, with FBCLK connected to FBIN, 15 pF load on
CLK0, and CLK0 > 60 MHz.
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
120
115
105
58
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
IDT™ / ICS™
QUADRACLOCK QUADRATURE DELAY BUFFER
5
ICS672-01/02
REV G 092506
