Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
F
EATURES
•
Six LVCMOS/LVTTL outputs, 20Ω nominal
output impedance
•
Output Q5 can be selected for ÷1 or ÷2 frequency relative
to the crystal frequency
•
Output frequency range: 12MHz to 40MHz
•
Crystal pull range: ± 90ppm (typical)
•
Synchronous output enable places outputs in High-Z state
•
On-chip filter on VIN to suppress noise modulation of VCXO
•
V
DD
/V
DDO
combinations
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
•
4mm x 4mm 20 Lead VFQFN package is ideal for space
constrained designs
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS81006I is a high performance, low
jitter/low phase noise VCXO and is a
HiPerClockS™
member of the HiPerClockS™ family of high
performance clock solutions from ICS. The
ICS81006I works in conjunction with a
pullable crystal to generate an output clock over the
range of 12MHz - 40MHz and has 6 LVCMOS outputs,
effectively integrating a fanout buffer function.
IC
S
The frequency of the VCXO is adjusted by the VC control
voltage input. The output range is ±100ppm around the
nominal crystal frequency. The VC control voltage range
is 0 - V
DD
. The device is packaged in a small 4mm x 4mm
VFQFN package and is ideal for use on space
constrained boards typically encountered in ADSL/
VDSL applications.
B
LOCK
D
IAGRAM
OE0
(Pullup)
P
IN
A
SSIGNMENT
GND
V
DDO
OE0
SYNC
Q0
Q0
VC
LP Filter
XTAL_IN
XTAL_OUT
1
2
3
4
5
20 19 18 17 16
15
14
13
12
6
OE1
Q1
GND
Q2
V
DDO
Q3
GND
Q1
XTAL_IN
V
DD
VC
VCXO
Q2
XTAL_OUT
Q3
DIV_SEL_Q5
7
GND
8
Q5
9
V
DDO
11
10
Q4
ICS81006I
Q4
20-Lead VFQFN
4mm x 4mm x 0.95 package body
K Package
Top View
0: ÷1
1: ÷2
DIV_SEL_Q5
(Pulldown)
Q5
OE1
(Pullup)
SYNC
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1
81006AKI
REV. A JANUARY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3
4
Name
XTAL_IN,
XTAL_OUT
V
DD
VC
Type
Input
Power
Input
Description
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Core supply pin.
Control voltage input.
Output divider select pin for Q5 output. When LOW, ÷1. When HIGH,
5
DIV_SEL_Q5 Input Pulldown
÷2, LVCMOS/LVTTL interface levels.
Output enable pin. When HIGH, Q5 output is enabled.
6
OE1
Input
Pullup
When LOW, forces Q5 to HiZ state. LVCMOS/LVTTL interface levels.
7, 11, 15, 19
GND
Power
Power supply ground.
8, 10, 12,
Q5, Q4, Q3,
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output
14, 16, 18
Q2, Q1, Q0
15
Ω
typical output impedance.
9, 13, 17
V
DDO
Power
Output supply pins.
Output enable pin. When HIGH, Q0:Q4 outputs are enabled. When
20
OE0
Input
Pullup
LOW, forces Q0:Q4 to HiZ state. LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
Parameter
Input Capacitance
OE0, OE1
V
DD
= V
DDO
= 3.465V
C
PD
Power Dissipation Capacitance
V
DD
= 3.465V or 2.625V,
V
DDO
= 2.625V
V
DD
= 3.465V or 2.625V,
V
DDO
= 2V
R
PULLUP
R
PULLDOWN
R
OUT
Input Pullup Resistor
Input Pulldown Resistor
V
DDO
= 3.3V
Output Impedance
V
DDO
= 2.5V
V
DDO
= 1.8V
51
51
20
25
38
Test Conditions
Minimum
Typical
4
3
4
6
Maximum
Units
pF
pF
pF
pF
kΩ
kΩ
Ω
Ω
Ω
81006AKI
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
38.5°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5% = 2.5V±5% = 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
1.6
Typical
3.3
3.3
2.5
1.8
Maximum
3.465
3.465
2.625
2.0
50
20
Units
V
V
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 2.5V±5% = 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
1.6
Typical
2.5
2.5
1.8
Maximum
2.625
2.625
2.0
50
20
Units
V
V
V
mA
mA
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
VC
I
IH
I
IL
I
I
V
OH
Parameter
Input High Voltage
Input Low Voltage
OE0, OE1,
DIV_SEL_Q5
DIV_SEL_Q5
OE0, OE1
DIV_SEL_Q5
OE0, OE1
Test Conditions
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V ± 5%
V
DD
= 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.3V or 2.5V ± 5%
V
DD
= 3.465V or 2.625V
V
DDO
= 3.3V ± 5%
Output High Voltage;NOTE 1
V
DDO
= 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
V
OL
Output Low Voltage;NOTE 1
V
DDO
= 3.3V or 2.5V ± 5%
V
DDO
= 1.8V ± 0.2V
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3
Minimum
2
1.7
-0.3
-0.3
0
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
V
DD
150
5
Units
V
V
V
V
V
µA
µA
µA
µA
VCXO Control Voltage
Input High Current
Input Low Current
-5
-150
-100
2.6
1.8
1.5
0.5
0.4
100
Input Current of VC pin
µA
V
V
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
81006AKI
REV. A JANUARY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
jit(Ø)
tsk(o)
t
R
/ t
F
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
Output Rise/Fall Time
Test Conditions
Minimum
12
Integration Range: 1kHz- 1MHz
Typical
19.44
0.35
30
DIV_SEL_Q5 = ÷1
20% to 80%
200
100
750
56
Maximum
40
Units
MHz
ps
ps
ps
ps
%
odc
Output Duty Cycle
44
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
jit(Ø)
tsk(o)
t
R
/ t
F
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
Output Rise/Fall Time
Test Conditions
Minimum
12
Integration Range: 1kHz- 1MHz
Typical
19.44
0.38
20
DIV_SEL_Q5 = ÷1
20% to 80%
300
90
800
55
Maximum
40
Units
MHz
ps
ps
ps
ps
%
odc
Output Duty Cycle
45
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4C. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
jit(Ø)
tsk(o)
t
R
/ t
F
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
Output Rise/Fall Time
Test Conditions
Minimum
12
Integration Range: 1kHz-1MHz
Typical
19.44
0.27
50
DIV_SEL_Q5 = ÷1
20% to 80%
45 0
180
1400
55
Maximum
40
Units
MHz
ps
ps
ps
ps
%
odc
Output Duty Cycle
45
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
81006AKI
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 19, 2006
Integrated
Circuit
Systems, Inc.
ICS81006I
VCXO-
TO
-6 LVCMOS O
UTPUTS
T
ABLE
4D. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
jit(Ø)
tsk(o)
t
R
/ t
F
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
Output Rise/Fall Time
Test Conditions
Minimum
12
Integration Range: 1kHz-1MHz
Typical
19.44
0.28
25
DIV_SEL_Q5 = ÷1
20% to 80%
300
105
800
55
Maximum
40
Units
MHz
ps
ps
ps
ps
%
odc
Output Duty Cycle
45
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4E. AC C
HARACTERISTICS
,
V
DD
= 2.5V±5%, V
DDO
= 1.8V±0.2V, T
A
= -40°C
TO
85°C
Symbol
f
OUT
t
jit(Ø)
tsk(o)
t
R
/ t
F
Parameter
Output Frequency
RMS Phase Jitter (Random);
NOTE 1
Q0:Q4
Output Skew;
NOTE 2, 3
Q0:Q5
Output Rise/Fall Time
Test Conditions
Minimum
12
Integration Range: 1kHz-1MHz
Typical
19.44
0.26
40
DIV_SEL_Q5 = ÷1
20% to 80%
45 0
185
1400
60
Maximum
40
Units
MHz
ps
ps
ps
ps
%
odc
Output Duty Cycle
40
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
81006AKI
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5
REV. A JANUARY 19, 2006
