PRELIMINARY
ICS840024I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
G
ENERAL
D
ESCRIPTION
The ICS840024I is a 4 output LVCMOS/LVTTL
ICS
Synthesizer optimized to generate Ethernet
HiPerClockS™
reference clock frequency and is a member of the
HiPerClocks
TM
family of high performance clock
solutions from ICS. The ICS840024I uses IDT’s
rd
3 generation low phase noise VCO technology and can
achieve 1ps or lower typical random rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS840024I is
packaged in a small 20-pin TSSOP package.
F
EATURES
• Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following output frequency: 125MHz
• RMS phase jitter @125MHz (1.875MHz - 20MHz):
0.60ps (typical)
• Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
B
LOCK
D
IAGRAM
OE Pullup
nPLL_SEL
nXTAL_SEL
XTAL_IN
Pulldown
Pulldown
25MHz
P
IN
A
SSIGNMENT
nc
nc
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
GND
Q0
Q1
V
DDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
OSC
XTAL_OUT
TEST_CLK Pulldown
0
1
Phase
Detector
Q0
1
VCO
Q1
0
÷5
Q2
ICS840024I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
M = ÷25 (fixed)
Q3
G Package
Top View
MR
Pulldown
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product
characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifica-
tions without notice.
840024AGI
1
REV. A DECEMBER 21, 2007
PRELIMINARY
ICS840024I
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 9, 20
3
4
5
6
Name
nc
nXTAL_SEL
TEST_CLK
OE
MR
Type
Unused
Input
Input
Input
Input
Pulldown
Pulldown
Pullup
Pulldown
Description
No connect.
Selects between the crystal or TEST_CLK inputs as the PLL reference
source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
Single-ended LVCMOS/LVTTL clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the otuputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency =
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Crystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Power supply ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
15
Ω
typical output impedence.
Output supply pin.
7
8
10
11,
12
13, 19
14, 15
17, 18
16
nPLL_SEL
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
GND
Q3, Q2,
Q1, Q0
V
DDO
Input
Power
Power
Input
Power
Output
Power
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
V
DD
, V
DDA
, V
DDO
= 3.465V
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
, V
DDA
= 3.465V, V
DDO
= 2.625V
V
DD
, V
DDA
, V
DDO
= 2.625V
Test Conditions
Minimum
Typical
4
TBD
TBD
TBD
51
51
15
Maximum
Units
pF
pF
pF
pF
KΩ
KΩ
Ω
840024AGI
2
REV. A DECEMBER 21, 2007
PRELIMINARY
ICS840024I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
75
6
3
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
75
6
3
Maximum
3.465
3.465
2.625
Units
V
V
V
mA
mA
mA
T
ABLE
3C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDD
= V
DDA
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
70
6
3
Maximum
2.625
2.625
2.625
Units
V
V
V
mA
mA
mA
840024AGI
3
REV. A DECEMBER 21, 2007
PRELIMINARY
ICS840024I
F
EMTO
C
LOCKS
™C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
3D. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%
OR
2.5V±5%,
OR
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
Input
High Voltage
Input
Low Voltage
Input
High Current
OE, MR,
nPLL_SEL, nXTAL_SEL,
TEST_CLK
OE, MR,
nPLL_SEL, nXTAL_SEL,
TEST_CLK
OE
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
OE
I
IL
Input
Low Current
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
V
DD
= V
IN
= 3.465V or
2.625V
V
DD
= V
IN
= 3.465V or
2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DDO
= 3.3V ± 5%
V
DDO
= 2.5V ± 5%
V
DDO
= 3.3V or 2.5V ± 5%
Test Conditions
Minimum Typical
2
2
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
5
150
-150
-5
2.6
1.8
0.5
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
IL
I
IH
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information, Output Load Test Circuit.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pf parallel resonant crystal.
Test Conditions
Minimum
Typical
25
50
7
Maximum
Units
MHz
Ω
pF
Fundamental
840024AGI
4
REV. A DECEMBER 21, 2007
PRELIMINARY
ICS840024I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
PLL Lock Time
Output Rise/Fall Time
Intergration Range
1.875MHz - 20MHz
20% to 80%
Test Conditions
Minimum
Typical
125
TBD
0.60
TBD
400
Maximum
Units
MHz
ps
ps
ms
ps
%
t
sk(o)
t
jit(Ø)
t
L
t
R
/ t
F
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
PLL Lock Time
Output Rise/Fall Time
Intergration Range
1.875MHz - 20MHz
20% to 80%
Test Conditions
Minimum
Typical
125
TBD
0.55
TBD
400
Maximum
Units
MHz
ps
ps
ms
ps
%
t
sk(o)
t
jit(Ø)
t
L
t
R
/ t
F
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
PLL Lock Time
Output Rise/Fall Time
Intergration Range
1.875MHz - 20MHz
20% to 80%
Test Conditions
Minimum
Typical
125
TBD
0.50
TBD
400
Maximum
Units
MHz
ps
ps
ms
ps
%
t
sk(o)
t
jit(Ø)
t
L
t
R
/ t
F
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840024AGI
5
REV. A DECEMBER 21, 2007
