WLAN and 3G/4G access and aggregation devices, storage
arrays, storage networking equipment, servers, and intelligent
NICs
802.11 a/b/g/n wireless for home data and multimedia
distribution
QoS for high quality Voice, Video, and Data service
Next-generationPON, VDSL2, and Cable networks
High-performance NAS
Audio/Video Storage and distribution
Consumer space media server
V
DD
nPLL_SEL
XTAL_IN
1
2
3
•
•
•
•
•
•
Pin Assignment
V
DDO_REF
QREF0
QREF1
QREF2
V
DDO_REF
GND
QC
V
DDO_C
32 31 30 29 28 27 26 25
24
V
DDO_B
QB
ICS840S06I
ICS8430S07I
32-Lead VFQFN
32-Lead VFQFN
5mm x 5mm x 0.75mm
5mm x 5mm x 0.75mm
package body
Package body
K Package
K Package
Top View
Top View
9
10 11 12 13 14 15 16
23
22
21
20
19
18
17
CORE_SEL
GND
GND
nOE_REF
XTAL_OUT 4
nXTAL_SEL
CLK
nCLK
GND
5
6
7
8
QA
V
DDO_A
PCI_SEL1
PCI_SEL0
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™
CLOCK GENERATOR
1
ICS840S06AKI REV. AI JULY 10, 2008
V
DDA
V
DD
nc
nc
nc
nc
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Block Diagram
nPLL_SEL
nXTAL_SEL
XTAL_IN
25 MHz
XTAL
XTAL_OUT
OSC
0
1
PLL
0 = 50.000 MHz
1 = 33.333 MHz
QA
Processor Core Clock
(LVCMOS)
0
1
00 = 133.333 MHz
01 = 100.000 MHz
10 = 66.667 MHz
11 = 33.333 MHz
125 MHz GbE CLK
25 MHz
CLK
nCLK
QB
PCI or PCI-X Clock
(LVCMOS)
Gigabit Ethernet MAC
Clock (LVCMOS)
QC
CORE_SEL
QREF0
PCI_SEL1:0
nOE_REF
Clock Output
Control Logic
25 MHz GbE CLK
\
\ Gigabit Ethernet
QREF1
/ PHY Clocks
/ (LVCMOS)
QREF2
IDT™ / ICS™
CLOCK GENERATOR
2
ICS840S06AKI REV. AI JULY 10, 2008
ICS840S06I
CLOCK GENERATOR FOR CAVIUM PROCESSORS
PRELIMINARY
Table 1. Pin Descriptions
Number
1, 15
2
3,
4
5
6
7
8, 20, 21, 27
9,
10
11, 12, 13, 14
16
17
18, 23, 26, 29,
30, 31
Name
V
DD
nPLL_SEL
XTAL_IN,
XTAL_OUT
nXTAL_SEL
CLK
nCLK
GND
PCI_SEL1,
PCI_SEL0
nc
V
DDA
V
DDO_A
QA, QB, QC,
QREF2,
QREF1, QREF0
nOE_REF
Power
Input
Input
Input
Input
Input
Power
Input
Unused
Power
Power
Output
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
Core supply pins.
PLL bypass. When LOW, selects PLL (PLL Enable). When HIGH, deselects
the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface.
XTAL_OUT is the output, XTAL_IN is the input.
Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK)
input when HIGH. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Power supply ground.
Selects the PCI/PCI-X reference clock output frequency. See Table 3B.
