PRELIMINARY
ICS842023I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS842023I is an Ethernet Clock
Generator and a member of the HiPerClocks
TM
HiPerClockS™
family of high performance devices from IDT.
For Ethernet applications, a 25MHz crystal is
used to generate 250MHz. The ICS842023I
uses IDT 3rd generation low phase noise VCO tech-
nology and can achieve <1ps r ms phase jitter, easily
meeting Ether net jitter requirements. The ICS842023I
is packaged in a small 8-pin TSSOP, making it ideal
for use in systems with limited board space.
F
EATURES
•
(1) Differential HSTL output
•
Crystal oscillator interface, 18pF parallel resonant crystal
(24.5MHz - 34MHz)
•
Output frequency range: 245MHz - 340MHz
•
VCO range: 490MHz - 680MHz
•
RMS phase jitter @ 250MHz, using a 25MHz crystal
(1.875Hz - 20MHz): 0.33ps (typical)
•
3.3V or 2.5V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
ICS
C
OMMON
C
ONFIGURATION
T
ABLE
- 1 Gb E
THERNET
Inputs
Crystal Frequency (MHz)
25
M
20
N
2
Multiplication
Value M/N
10
Output Frequency
(MHz)
250
B
LOCK
D
IAGRAM
OE
Pullup
P
IN
A
SSIGNMENT
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q0
nQ0
OE
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
490MHz - 680MHz
N = ÷2
(fixed)
Q0
nQ0
ICS842023I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
G Package
Top View
M = ÷20
(fixed)
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product
characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifica-
tions without notice.
842023AGI
1
REV. B JANUARY 18, 2008
PRELIMINARY
ICS842023I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4
5
6, 7
8
Name
V
DDA
GND
XTAL_OUT,
XTAL_IN
OE
nQ0, Q0
V
DD
Power
Power
Input
Input
Output
Power
Pullup
Type
Description
Analog supply pin.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Output enable pin. When HIGH, Q0/nQ0 output is active.
When LOW, the Q0/nQ0 output is in a high impedance state.
LVCMOS/LVTTL interface levels.
Differential clock outputs. HSTL interface levels.
Core supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
842023AGI
2
REV. B JANUARY 18, 2008
PRELIMINARY
ICS842023I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
101.7°C/W (0 mps)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
TBD
TBD
Maximum
3.465
3.465
Units
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
2.375
Typical
2.5
2.5
TBD
TBD
Maximum
2.625
2.625
Units
V
V
mA
mA
T
ABLE
3C. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
OE
OE
Test Conditions
3.3V
2.5V
3.3V
2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
842023AGI
3
REV. B JANUARY 18, 2008
PRELIMINARY
ICS842023I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
T
ABLE
3D. HSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
OX
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Test Conditions
Minimum
1
0
40
0.4
Typical
Maximum
1.8
0.6
60
1.8
Units
V
V
%
V
V
SWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to GND.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
3E. HSTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
OH
V
OL
V
OX
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output Crossover Voltage; NOTE 2
Test Conditions
Minimum
1
0
40
0.6
Typical
Maximum
1.4
0.4
60
1.4
Units
V
V
%
V
V
SWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50
Ω
to GND.
NOTE 2: Defined with respect to output voltage swing at a given condition.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
24.5
Test Conditions
Minimum
Typical
Fundamental
34
50
7
1
MH z
Ω
pF
mW
Maximum
Units
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
250MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
Minimum
245
0.33
300
50
Typical
Maximum
340
Units
MH z
ps
ps
%
t
jit(Ø)
t
R
/ t
F
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
f
OUT
Parameter
Output Frequency
RMS Phase Jitter ( Random);
NOTE 1
Output Rise/Fall Time
Test Conditions
250MHz @ Integration Range:
1.875MHz - 20MHz
20% to 80%
Minimum
245
0.4
325
50
Typical
Maximum
340
Units
MH z
ps
ps
%
t
jit(Ø)
t
R
/ t
F
odc
Output Duty Cycle
NOTE 1: Please refer to the Phase Noise Plots following this section.
842023AGI
4
REV. B JANUARY 18, 2008
PRELIMINARY
ICS842023I
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
- HSTL
C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V ± 5%
2.5V ± 5%
V
DD,
V
DDA
Qx
SCOPE
V
DD,
V
DDA
Qx
SCOPE
HSTL
nQx
HSTL
nQx
GND
GND
0V
0V
HSTL 3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
HSTL 2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
Phase Noise Plot
nQ0
Noise Power
Q0
t
PW
Phase Noise Mask
t
PERIOD
odc =
f
1
Offset Frequency
f
2
t
PW
t
PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS P
HASE
J
ITTER
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
80%
Clock
Outputs
80%
V
SW I N G
20%
t
R
t
F
20%
O
UTPUT
R
ISE
/F
ALL
T
IME
842023AGI
5
REV. B JANUARY 18, 2008
