PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843101I-312
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-LVPECL
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
F
EATURES
• One 312.5MHz nominal LVPECL output
• Selectable crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal or LVCMOS/LVTTL
single-ended input
• Output frequency can be varied in 2% steps ± from
nominal
• VCO range: 560MHz - 690MHz
• RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.52ps (typical)
• Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-complaint
packages
G
ENERAL
D
ESCRIPTION
The ICS843101I-312 is a low phase-noise
frequency margining synthesizer with fre-
HiPerClockS™
quency margining capability and is a member of
the HiPerClockS™ family of high performance
clock solutions from ICS. In the default mode,
the device nominally generates a 312.5MHz LVPECL output
clock signal from a 25MHz crystal input. There is also a
frequency margining mode available where the device can
be programmed, using the serial interface, to vary the
output frequency up or down from nominal in 2% steps.
The ICS843101I-312 is provided in a 16-pin TSSOP.
IC
S
B
LOCK
D
IAGRAM
OE
CLK
Pullup
Pulldown
P
IN
A
SSIGNMENT
V
EE
S_LOAD
S_DATA
Q S_CLOCK
SEL
nQ
OE
V
CCA
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
MODE
V
CCO
Q
nQ
V
EE
CLK
XTAL_OUT
XTAL_IN
1
25MHz
÷P
OSC
0
XTAL_IN
XTAL_OUT
SEL
Phase
Detector
VCO
560 - 690MHz
÷N
Pulldown
÷M
ICS843101I-312
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
S_CLOCK
S_DATA
S_LOAD
MODE
Pulldown
Pulldown
Pulldown
Pulldown
Serial Control
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843101AGI-312
www.icst.com/products/hiperclocks.html
1
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843101I-312
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-LVPECL
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
some values of M (either too high or too low), the PLL will
not achieve lock. The output of the VCO is scaled by an
output divider prior to being sent to the LVPECL output
buffer. The divider provides a 50% output duty cycle. The
relationship between the crystal input frequency, the M
divider, the VCO frequency and the output frequency
is provided in Table 1. When changing back from fre-
quency margining mode to nominal mode, the device will
return to the default nominal configuration that will provide
312.5 MHz output frequency.
Serial operation occurs when S_LOAD is HIGH. Serial
data can be loaded in either the default mode or the fre-
quency margining mode. The 6-bit shift register is loaded
by sampling the S_DATA bits with the rising edge of
S_CLOCK. After shifting in the 6-bit M divider value,
S_LOAD is transitioned from HIGH to LOW which latches
the contents of the shift-register into the M divider control
register. When S_LOAD is LOW, any transitions of
S_CLOCK or S_DATA are ignored.
F
UNCTIONAL
D
ESCRIPTION
The ICS843101I-312 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A 25MHz fundamental crystal is used as
the input to the on chip oscillator. The output of the osc-
illator is fed into the pre-divider. In frequency margining
mode, the 25MHz crystal frequency is divided by 2 and
a 12.5MHz reference frequency is applied to the phase
detector. The VCO of the PLL operates over a range of
560MHz to 690MHz. The output of the M divider is also
applied to the phase detector.
The default mode for the ICS843101I-312 is 312.5MHz
output frequency using a 25MHz crystal. The output fre-
quency can be changed by placing the device into the
margining mode using the mode pin and using the serial
interface to program the M feedback divider. Frequency
margining mode operation occurs when the MODE input
is HIGH. The phase detector and the M divider force the
VCO output frequency to be M times the reference fre-
quency by adjusting the VCO control voltage. Note that for
T
ABLE
1. F
REQUENCY
M
ARGIN
F
UNCTION
T
ABLE
XTAL
(MHz)
25
25
25
25
25
25
25
25
25
25
25
Pre-Divider
(P)
2
2
2
2
2
2
2
2
2
2
2
Reference
Frequency (MHz)
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
Feedback
Divider (M)
45
46
47
48
49
50
51
52
53
54
55
M-Data
(Binary)
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
VCO
(MHz)
562.5
575
587.5
600
612.5
625
637.5
650
662.5
675
687.5
Output
Divider (N)
2
2
2
2
2
2
2
2
2
2
2
Output
Frequency
(MHz)
281.25
287.5
293.75
300
306.25
312.5
318.75
325
331.25
337.5
343.75
% Change
-10.0
-8.0
-6.0
-4.0
-2.0
Nominal Mode
2.0
4. 0
6.0
8.0
10.0
S
ERIAL
L
OADING
S_CLOCK
S_DATA
M5 M4
t
S
M3
M2
M1
M0
t
S
t
H
S_LOAD
Time
F
IGURE
1. S
ERIAL
L
OAD
O
PERATIONS
843101AGI-312
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843101I-312
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-LVPECL
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
Τψπ ε
Δ ε σχριπ τιο ½
Negative supply pins.
Pulldown Controls the operation of the Serial input. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
Pulldown
LVCMOS/LVTTL interface levels.
Clock in serial data present at S_DATA input into the shift register on the
Pulldown
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Select pin. When HIGH, selects CLK input.
Pulldown
When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels.
Output enable pin. Controls enabling and disabling of Q/nQ outputs.
Pullup
LVCMOS/LVTTL interface levels
Analog supply pin.
Core supply pin.
Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
Pulldown LVCMOS/LVTTL clock input.
Differential output pair. LVPECL interface levels.
T
ABLE
2. P
IN
D
ESCRIPTIONS
Νυ μ β ε ρ
1, 12
2
3
4
5
6
7
8
9, 10
11
13, 14
15
Ναμ ε
V
EE
S_LOAD
S_DATA
S_CLOCK
SEL
OE
V
CCA
V
CC
XTAL_IN,
XTAL_OUT
CLK
nQ, Q
V
CCO
Input
Input
Input
Input
Input
Power
Power
Input
Input
Ouput
Power
Power
Output supply pin.
MODE pin. LOW = default mode. HIGH = frequency margining mode.
16
MODE
Input
Pulldown
LVCMOS/LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
3. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
843101AGI-312
www.icst.com/products/hiperclocks.html
3
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843101I-312
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-LVPECL
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
T
ABLE
4A. OE C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
OE
0
1
Outputs
Q , nQ
HiZ
Enabled
T
ABLE
4B. SEL C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
SEL
0
1
Selected Source
XTAL_IN, XTAL_OUT
CLK
T
ABLE
4C. M
ODE
C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Input
Mode
0
1
Condition
Q, nQ
Default Mode
Frequency Margining Mode
T
ABLE
4D. S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
S_LOAD
L
H
S_CLOCK
X
↑
S_DATA
X
Data
Serial inputs are ignored.
Serial input mode.
Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are latched.
Conditions
L
X
↓
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
843101AGI-312
www.icst.com/products/hiperclocks.html
4
REV. A NOVEMBER 1, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS843101I-312
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-LVPECL
312.5MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
89°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CC
I
CCA
I
CCO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Core Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
92
78
7
4
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
mA
T
ABLE
5B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%,V
CCO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CC
I
CCA
I
CCO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Core Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
90
78
7
4
Maximum
3.465
3.465
2.625
Units
V
V
V
mA
mA
mA
mA
T
ABLE
5C. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 2.5V±5%, T
A
= -40°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CC
I
CCA
I
CCO
843101AGI-312
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Core Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
2.375
2.375
Typical
2.5
2.5
2.5
84
74
7
3
Maximum
2.625
2.625
2.625
Units
V
V
V
mA
mA
mA
mA
www.icst.com/products/hiperclocks.html
5
REV. A NOVEMBER 1, 2005
