Integrated
Circuit
Systems, Inc.
ICS84314
350MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W
/F
ANOUT
B
UFFER
F
EATURES
•
Fully integrated PLL
•
4 differential 3.3V or 2.5V LVPECL outputs
•
Selectable crystal oscillator interface
or LVCMOS TEST_CLK input
•
Output frequency range: 62.5MHz to 350MHz
•
VCO range: 250MHz to 700MHz
•
Parallel interface for programming counter
and output dividers during power-up
•
Serial 3 wire interface
•
Cycle-to-cycle jitter: 23ps (typical)
•
Output skew: 16ps (typical)
•
Output duty cycle: 49% < odc < 51%, fout
≤
125MHz
•
Full 3.3V or mixed 3.3V core, 2.5V operating supply
•
0°C to 85°C ambient operating temperature
•
Lead-Free package available
G
ENERAL
D
ESCRIPTION
The ICS84314 is a general purpose quad output
frequency synthesizer and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from ICS. When the device uses par-
allel loading, the M bits are programmable and
the output divider is hard-wired for divide by 2 thus providing
a frequency range of 125MHz to 350MHz. In serial program-
ming mode, the M bits are programmable and the output di-
vider can be set for either divide by 2 or divide by 4, providing
a frequency range of 62.5MHz to 350MHz. The low cycle-
cycle jitter and broad frequency range of the ICS84314 make
it an ideal clock generator for a variety of demanding applica-
tions which require high performance.
ICS
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL2
XTAL1
M3
M2
M1
M0
VCO_SEL
32 31 30 29 28 27 26 25
XTAL_SEL
M4
TEST_CLK
XTAL1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
24
23
22
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
V
CCO
0
M5
M6
OSC
XTAL2
1
÷
16
M7
M8
V
EE
V
CC
ICS84314
21
20
19
18
17
PLL
PHASE DETECTOR
MR
V
CCO
Q0
nQ0
0
1
VCO
÷
M
÷
2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
÷2
÷4
Q1
nQ1
Q2
nQ2
Q3
nQ3
CONFIGURATION
INTERFACE
LOGIC
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
84314AY
www.icst.com/products/hiperclocks.html
1
REV. C JANUARY 27, 2005
Integrated
Circuit
Systems, Inc.
ICS84314
350MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W
/F
ANOUT
B
UFFER
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 is passed directly to the M divider. On the LOW-to-HIGH tran-
sition of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or until
a serial event occurs. As a result, the M bits can be hardwired to
set the M divider to a specific default state that will automatically
occur during power-up. In parallel mode, the N output divider is
set to 2. In serial mode, the N output divider can be set for either
÷2
or
÷4.
The relationship between the VCO frequency, the crys-
tal frequency and the M divider is defined as follows:
fxtal x 2M
fVCO =
16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16MHz refer-
ence are defined as 125
≤
M
≤
350. The frequency out
is defined as follows: fout = fVCO x 1 = fxtal x 2M x 1
N 16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift regis-
ter are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N out-
put divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each
rising edge of S_CLOCK.
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes
operation using a 16MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS84314 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A parallel-resonant, fundamental crystal is used
as the input to the on-chip oscillator. The output of the os-
cillator is divided by 16 prior to the phase detector. With a
16MHz crystal, this provides a 1MHz reference frequency.
The VCO of the PLL operates over a range of 250MHz to
700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by ad-
justing the VCO control voltage. Note that for some values
of M (either too high or too low), the PLL will not achieve
lock. The output of the VCO is scaled by a divider prior to
being sent to each of the LVPECL output buffers. The divider
provides a 50% output duty cycle.
The programmable features of the ICS84314 support two
input modes to program the M divider. The two input op-
erational modes are parallel and serial.
Figure 1
shows
the timing diagram for each mode. In parallel mode, the
S
ERIAL
L
OADING
S_CLOCK
S_DATA
S_LOAD
*NULL *NULL *NULL *NULL
t
S
**N
M8
M7
M6
M5
M4
M3
M2
M1
M0
t
H
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M8
M
nP_LOAD
t
S
t
H
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
T
ABLE
1. N O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
(S
ERIAL
L
OAD
)
N Logic Value
0
1
Output Divide
÷2
÷4
*NOTE:
The NULL timing slot must be observed.
**NOTE:
“N” can only be controlled through serial loading.
84314AY
www.icst.com/products/hiperclocks.html
2
REV. C JANUARY 27, 2005
Integrated
Circuit
Systems, Inc.
ICS84314
350MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W
/F
ANOUT
B
UFFER
Type
Input
Input
Power
Power
Power
Output
Output
Output
Output
Description
T
ABLE
2. P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 4,
29, 30, 31, 32
5
6
7
8, 17
9, 10
11, 12
13, 14
15, 16
Name
M4, M5, M6, M7,
M0, M1, M2, M3
M8
V
EE
V
CC
V
CCO
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Pulldown M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
Pullup
Negative supply pin.
Core power supply pin.
Output supply pins.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs Qx to go low and the inver ted
18
MR
Input Pulldown outputs nQx to go high. When logic LOW, the internal dividers and
the outputs are enabled. Asser tion of MR does not affect loaded
M values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
19
S_CLOCK
Input Pulldown
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
20
S_DATA
Input Pulldown
of S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
21
S_LOAD
Input Pulldown
LVCMOS / LVTTL interface levels.
22
V
CCA
Power
Analog supply pin.
Selects between the crystal oscillator or test clock as the PLL
23
XTAL_SEL
Input
Pullup reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
24
TEST_CLK
Input Pulldown Test clock input. LVCMOS interface levels.
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
25, 26
XTAL1, XTAL2
Input
Parallel load input. Determines when data present at M8:M0
27
nP_LOAD
Input Pulldown
is loaded into the M divider. LVCMOS / LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
28
VCO_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
3. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
84314AY
www.icst.com/products/hiperclocks.html
3
REV. C JANUARY 27, 2005
Integrated
Circuit
Systems, Inc.
ICS84314
350MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W
/F
ANOUT
B
UFFER
T
ABLE
4A. P
ARALLEL
AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
Conditions
S_CLOCK
X
X
X
↑
L
L
X
↑
S_DATA
X
X
X
Data
Data
Data
X
Data
Reset. Forces outputs LOW.
Data on M inputs passed directly to the M divider.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
MR
H
L
L
L
L
L
L
nP_LOAD
X
L
↑
H
H
H
H
M
X
Data
Data
X
X
X
X
S_LOAD
X
X
L
L
↑
↓
L
L
H
X
H
NOTE: L = LOW
H = HIGH
X = Don't care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
4B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
VCO Frequency
(MHz)
250
252
254
256
•
•
696
698
M Divide
125
126
127
128
•
•
348
349
256
M8
0
0
0
0
•
•
1
1
128
M7
0
0
0
1
•
•
0
0
64
M6
1
1
1
0
•
•
1
1
32
M5
1
1
1
0
•
•
0
0
16
M4
1
1
1
0
•
•
1
1
8
M3
1
1
1
0
•
•
1
1
4
M2
1
1
1
0
•
•
1
1
2
M1
0
1
1
0
•
•
0
0
1
M0
1
0
1
0
•
•
0
1
700
350
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input
frequency of 16MHz.
T
ABLE
4C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
(S
ERIAL
P
ROGRAMMING
M
ODE
O
NLY
)
Input
N Logic
0
1
N Divide
2
4
Output Frequency (MHz)
Qx, nQx
Minimum
Maximum
12 5
350
62.5
175
84314AY
www.icst.com/products/hiperclocks.html
4
REV. C JANUARY 27, 2005
Integrated
Circuit
Systems, Inc.
ICS84314
350MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER W
/F
ANOUT
B
UFFER
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
5A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
85°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
2.375
Typical
3.3
3.3
3.3
2.5
Maximum
3.465
3.465
3.465
2.625
150
17
Units
V
V
V
V
mA
mA
T
ABLE
5B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
85°C
Symbol
Input
High Voltage
Parameter
TEST_CLK; NOTE 1
V
IH
VCO_SEL, XTAL_SEL,
nP_LOAD, MR, M0:M8,
S_LOAD, S_DATA, S_CLOCK
TEST_CLK; NOTE 1
V
IL
Input
Low Voltage
VCO_SEL, XTAL_SEL,
nP_LOAD, MR, M0:M8,
S_LOAD, S_DATA, S_CLOCK
M0:M7, MR, nP_LOAD,
S_CLOCK, S_DATA,
S_LOAD
M8, XTAL_SEL, VCO_SEL
TEST_CLK
M0:M7, MR, nP_LOAD,
S_CLOCK, S_DATA,
S_LOAD
M8, XTAL_SEL, VCO_SEL
NOTE:1 Characterized with 1ns input edge rate.
Test Conditions
Minimum
2.35
2
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
V
CC
+ 0.3
0.95
0.8
Units
V
V
V
V
I
IH
Input
High Current
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V,
V
IN
= 0V
V
CC
= 3.465V,
V
IN
= 0V
-5
-150
150
5
200
µA
µA
µA
µA
µA
I
IL
Input
Low Current
84314AY
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5
REV. C JANUARY 27, 2005
