PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84334
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
•
Dual differential 3.3V LVPECL outputs which can be set
independently for either 3.3V or 2.5V
•
4:1 Input Mux:
1 differential input
1 single-ended input
2 crystal oscillator interfaces
•
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
TEST_CLK accepts LVCMOS or LVTTL input levels
•
Output frequency range: 31.25MHz to 700MHz
•
Crystal input frequency range: 12MHz to 40MHz
•
VCO range: 500MHz to 700MHz
•
Parallel or serial interface for programming feedback divider
and output dividers
•
RMS phase jitter at 106.25MHz, using a 25.5MHz crystal
(637KHz to 5MHz): 2.31ps (typical)
Phase noise: 106.25MHz (typical), using a 25.5MHz crystal
Offset
Noise Power
100Hz ....................... -86 dBc/Hz
1KHz ..................... -111 dBc/Hz
10KHz ..................... -125 dBc/Hz
100KHz ..................... -130 dBc/Hz
•
Supply voltage modes:
LVPECL outputs (core/outputs):
3.3V/3.3V
3.3V/2.5V
REF_CLK output (core/outputs):
3.3V/3.3V
•
0°C to 70°C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS84334 is a general purpose, low phase
noise LVPECL synthesizer which can generate
HiPerClockS™
frequencies for a wide variety of applications. The
ICS84334 has a 4:1 input Multiplexer from which
the following inputs can be selected: 1 differential
input, 1 single-ended input, or two crystal oscillators,
thus making the device ideal for frequency translation or
frequency generation. Each differential LVPECL output pair has
an output divider which can be independently set so that two
different frequencies can be generated. Additionally, each
LVPECL output pair has a dedicated power supply pin so the
outputs can run at 3.3V or 2.5V. The ICS84334 also supplies a
buffered copy of the reference clock or crystal frequency on the
single-ended REF_CLK pin which can be enabled or disabled
(disabled by default). The output frequency can be programmed
using either a serial or parallel programming interface.
ICS
The phase noise/phase jitter of the ICS84334 is excellent and
is expected to be in the 2-5ps rms range, thus making it
suitable for use in Fibre Channel, SONET, and Ethernet/1Gb
Ethernet applications.
Example applications include systems which must support both
FEC and non FEC rates. In 10 Gb Fibre Channel, for example,
you can use a 25.5MHz crystal to generate a 159.375MHz
reference clock, and then switch to a 20.544MHz crystal to
generate 164.355MHz for 66/64 FEC. Other applications could
include supporting both Ethernet frequencies and SONET
frequencies in an application. When Ethernet frequencies are
needed, a 25MHz crystal can be used and when SONET
frequencies are needed, the input MUX can be switched to select
a 38.88MHz Crystal.
P
IN
A
SSIGNMENT
CLK
nCLK
nP_LOAD
VCO_SEL
M0
M1
M2
M3
M4
M5
NA0
NA1
NA2
NB0
NB1
NB2
OE_REF
OE_A
OE_B
V
CC
nc
nc
nc
V
EE
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
48-Pin LQFP
6
31
7mm x 7mm x 1.4mm
7
30
package body
8
29
Y Package
9
28
Top View
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS84334
XTAL_OUT1
XTAL_IN1
XTAL_OUT0
XTAL_IN0
TEST_CLK
SEL1
SEL0
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84334BY
V
EE
nc
V
CCO
_
REF
REF_CLK
V
CCOB
nFOUTB0
FOUTB0
V
CCOA
nFOUTA0
FOUTA0
V
CC
TEST
www.icst.com/products/hiperclocks.html
1
REV. A JULY 22, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84334
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
B
LOCK
D
IAGRAM
OE_A
VCO_SEL
XTAL_IN0
OSC
XTAL_OUT0
XTAL_IN1
XTAL_OUT1
00
OSC
01
0
000
001
010
011
100
101
110
111
÷
1
÷
2
÷
3
÷
4
÷
5
÷
6
÷
8
÷16
FOUTA0
nFOUTA0
V
CCO_A
CLK
nCLK
10
P
HASE
D
ETECTOR
VCO
1
TEST_CLK
11
÷
M
000
001
010
011
100
101
110
111
÷
1
÷
2
÷
3
÷
4
÷
5
÷
6
÷
8
÷16
V
CCO_B
FOUTB0
nFOUTB0
SEL1
SEL0
OE_B
MR
V
CCO_REF
REF_CLK
OE_REF
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M5:M0
NA2:NA0
NB2:NB0
CONFIGURATION
INTERFACE
LOGIC
TEST
84334BY
www.icst.com/products/hiperclocks.html
2
REV. A JULY 22, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84334
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS84334 features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 500MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84334 support two
input modes to program the M divider and Nx output divider. The
two input operational modes are parallel and serial.
Figure 1
shows the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on the M, NA, and NB
inputs are passed directly to the M divider and both N output
dividers. On the LOW-to-HIGH transition of the nP_LOAD in-
put, the data is latched and the M and N dividers remain loaded
until the next LOW transition on nP_LOAD or until a serial event
occurs. As a result, the M and Nx bits can be hardwired to set
the M divider and Nx output divider to a specific default state
that will automatically occur during power-up. The TEST output
is LOW when operating in the parallel input mode. The relation-
ship between the VCO frequency, the crystal frequency and the
M divider is defined as follows:
fVCO = fxtal x M
The M value and the required values of M0 through M5 are shown
in Table 3B to program the VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 25MHz
reference are defined as 25
≤
M
≤
31. The frequency out is de-
fined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and Nx output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and Nx output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and Nx
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and Nx bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1 T0
TEST Output
0
0
1
1
0
1
0
1
LOW
S_Data, Shift Register Output
Output of M divider
CMOS Fout A0
S
ERIAL
L
OADING
S_CLOCK
S_DATA
t
T1
S
T0
NB2
NB1 NB0
NA2
NA1
NA0
M5
M4
M3
M2
M1
M0
t
S_LOAD
H
nP_LOAD
t
S
P
ARALLEL
L
OADING
M0:M5,
NA0:NA2, NB0:NB2
nP_LOAD
t
S
M, N
t
H
Time
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
84334BY
www.icst.com/products/hiperclocks.html
3
REV. A JULY 22, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84334
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 3
4
5
6
7
8, 14
9, 10, 11,
23
12, 24
13
15, 16
17
18, 19
20
21
22
Name
NA 2
NB0, NB1
NB2
OE_REF
OE_A
OE _B
V
CC
nc
V
EE
TEST
FOUTA0,
nFOUTA0
V
CCOA
FOUTB0,
nFOUTB0
V
CCOB
REF_CLK
V
CCO_REF
Input
Input
Input
Input
Input
Input
Power
Unused
Power
Output
Output
Power
Output
Power
Output
Power
Type
Description
Determines output divider value as defined in Table 3C,
Pulldown
Function Table. LVCMOS/LVTTL interface levels.
Pullup
Determines output divider value as defined in Table 3C,
Pulldown Function Table. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of REF_CLK output.
LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTA0,
nFOUTA0 outputs. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of FOUTB0,
nFOUTB0 outputs. LVCMOS/LVTTL interface levels.
Core supply pins.
No connect.
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode.
LVCMOS/LVTTL interface levels.
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTA0, nFOUTA0.
Differential output for the synthesizer. LVPECL interface levels.
Output supply pin for FOUTB0, nFOUTB0.
Reference clock output. LVCMOS/LVTTL interface levels.
Output supply pin for REF_CLK.
Active High Master Reset. When logic HIGH, forces the internal
dividers are reset causing the true outputs FOUTx to go low and the
inver ted outputs nFOUTx to go high. When logic LOW, the internal
dividers and the outputs are enabled. Asser tion of MR does not
affect loaded M, N, and T values. LVCMOS/LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS/LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Pulldown
Pullup
Pullup
25
MR
Input
Pulldown
26
27
28
29
30, 31
32
33, 34
35, 36
37
38
S_CLOCK
S_DATA
S_LOAD
V
CCA
SEL0, SEL1
TEST_CLK
XTAL_IN0,
XTAL_OUT0
XTAL_IN1,
XTAL_OUT1
CLK
nCLK
Input
Input
Input
Power
Input
Input
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.
Pulldown Test clock input. LVCMOS/LVTTL interface levels.
Cr ystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
Cr ystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1 is the output.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input.V
CC
/2 default when left floating.
Pulldown
Continued on next page...
84334BY
www.icst.com/products/hiperclocks.html
4
REV. A JULY 22, 2004
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS84334
M
ULTI
-R
ATE
LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
(continued from previous page)
Number
39
Name
nP_LOAD
Input
Type
Description
Parallel load input. Determines when data present at M5:M0 is
loaded into M divider, and when data present at NA2:NA0 and
Pulldown
NB2:NB0 is loaded into the N output dividers.
LVCMOS/LVTTL interface levels.
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS/LVTTL interface levels.
Pullup
40
41, 44, 45
VCO_SEL
M0, M3, M4
Input
Input
M divider inputs. Data latched on LOW-to-HIGH transition
42, 43, 46
M1, M2, M5
Input
Pulldown of nP_LOAD input. LVCMOS/LVTTL interface levels.
Determines output divider value as defined in Table 3C,
47, 48
NA0, NA1
Input
Pullup
Function Table. LVCMOS/LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
5
Test Conditions
Minimum
Typical
4
51
51
7
12
Maximum
Units
pF
KΩ
KΩ
Ω
84334AY
www.icst.com/products/hiperclocks.html
5
REV. A SEPTEMBER 25, 2003
