• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
The two banks have their own dedicated frequency select pins
and can be independently set for the frequencies mentioned
above. The ICS844003-01 uses IDT’s 3rd generation low phase
noise VCO technology and can achieve 1ps or lower typical rms
phase jitter, easily meeting Ethernet jitter requirements. The
ICS844003-01 is packaged in a small 24-pin TSSOP package.
P
IN
A
SSIGNMENT
DIV_SELB0
VCO_SEL
MR
V
DDO
_
A
QA0
nQA0
OEB
OEA
FB_DIV
V
DDA
V
DD
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
V
DDO
_
B
QB0
nQB0
QB1
nQB1
XTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
GND
DIV_SELA1
B
LOCK
D
IAGRAM
CLK_ENA
Pullup
DIV_SELA[1:0]
Pullup
VCO_SEL
Pullup
ICS844003-01
QA0
TEST_CLK
Pulldown
0
0
00
01
10
11
÷1
÷2
÷3
÷4
(default)
nQA0
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
1
QB0
FB_DIV
0 = ÷25 (default)
1 = ÷32
00
01
10
11
÷2
÷4
÷5
÷8
(default)
nQB0
QB1
nQB1
FB_DIV
Pulldown
DIV_SELB[1:0]
Pullup
MR
Pulldown
CLK_ENB
Pullup
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product
characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
LVDS FREQUENCY SYNTHESIZER
1
ICS844003CG-01 REV A OCTOBER 31, 2006
ICS844003-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Νυ µ β ε ρ
Number
1,
24
2
Ναµ ε
Name
DIV_SELB0,
DIV_SELB1
VCO_SEL
Τψπ ε
Type
Input
∆ ε σχριπ τιο ½
Description
Division select pin for Bank B. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels. See Table 3C.
VCO select pin. When Low, the PLL is bypassed and the crystal reference
or REF_CLK (depending on XTAL_SEL setting) are passed directly to the
Pullup
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state
of outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
Output enable Bank B. Active High outputs are enable. When logic HIGH,
the output pairs on Bank B are enabled. When logic LOW, the output pairs
are in a high impedance state. Has an internal pullup resistor so the default
power-up state of outputs are enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH,
the output pair in Bank A is enabled. When logic LOW, the output pair is in
a high impedance state. Has an internal pullup resistor so the default
power-up state of output is enabled. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set
for ÷25. When HIGH, the feedback divider is set for ÷32.
LVCMOS/LVTTL interface levels. See Table 3D.
Analog supply pin.
Input
3
MR
Input
4
5, 6
7
V
DDO_A
QA0, nQA0
OE B
Power
Ouput
Input
Pullup
8
OEA
Input
Pullup
9
10
11
12,
13
14
15,
16
17
FB_DIV
V
DDA
V
DD
DIV_SELA0,
DIV_SELA1
GND
XTAL_OUT,
XTAL_IN
REF_CLK
Input
Power
Power
Input
Power
Input
Pulldown
Input
18
19, 20
21, 22
XTAL_SEL
nQB1, QB1
nQB0, QB0
Input
Output
Output
Core supply pin.
Division select pin for Bank A. Default = HIGH.
Pullup
LVCMOS/LVTTL interface levels. See Table 3C.
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal
circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to
Pulldown pull to low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended REF_CLK or crystal
Pullup
interface. Has an internal pullup resistor so the crystal interface is selected
by default. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Power
Output supply pin for Bank B outputs.
23
V
DDO_B
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
LVDS FREQUENCY SYNTHESIZER
2
ICS844003CG-01 REV A OCTOBER 31, 2006
ICS844003-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
3A. B
ANK
A F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
(MHz)
25
25
20
22.5
25
24
20
19.44
19.44
15.625
18.75
19.44
18.75
15.625
FB_DIV
0
0
0
0
0
0
0
1
1
1
1
1
1
1
DIV_SELA1 DIV_SELA0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
Feedback
Divider
25
25
25
25
25
25
25
32
32
32
32
32
32
32
Bank A
Output Divider
1
2
2
3
4
4
4
1
2
2
3
4
4
4
M/N
Multiplication
Factor
25
12.5
12.500
8.333
6.25
6.25
6.25
32
16
16
10.667
8
8
8
QA0/nQA0
Output
Frequency
(MHz)
62 5
312.5
250
187.5
156.25
150
125
622.08
311.04
25 0
200
155.52
15 0
12 5
T
ABLE
3B. B
ANK
B F
REQUENCY
T
ABLE
Inputs
Crystal Frequency
(MHz)
25
20
25
24
20
25
25
24
20
19.44
15.625
19.44
18.75
15.625
15.625
19.44
18.75
15.625
FB_DIV
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
DIV_SELB1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
DIV_SELB0
0
0
1
1
1
0
1
1
1
0
0
1
1
1
0
1
1
1
Feedback
Divider
25
25
25
25
25
25
25
25
25
32
32
32
32
32
32
32
32
32
Bank B
Output Divider
2
2
4
4
4
5
8
8
8
2
2
4
4
4
5
8
8
8
M/N
Multiplication
Factor
12.5
12.5
6.25
6.25
6.25
5
3.125
3.125
3.125
16
16
8
8
8
6.4
4
4
4
QBx/nQBx
Output
Frequency
(MHz)
312.5
250
156.25
150
12 5
125
78.125
75
62.5
311.04
250
155.52
150
125
10 0
77.76
75
62.5
IDT
™
/ ICS
™
LVDS FREQUENCY SYNTHESIZER
3
ICS844003CG-01 REV A OCTOBER 31, 2006
ICS844003-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
T
ABLE
3C. O
UTPUT
B
ANK
A C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
DIV_SELA1
0
0
1
1
DIV_SELA0
0
1
0
1
Outputs
QA0, nQA0
÷1
÷2
÷3
÷4 (default)
T
ABLE
3D. O
UTPUT
B
ANK
B C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
DIV_SELB1
0
0
1
1
DIV_SELB0
0
1
0
1
Outputs
QBx, nQBx
÷2
÷4
÷5
÷8 (default)
T
ABLE
3E. F
EEDBACK
D
IVIDER
C
ONFIGURATION
S
ELECT
F
UNCTION
T
ABLE
Inputs
FB_DIV
0
1
Feedback Divide
÷2 5
÷32
T
ABLE
3F. OEA S
ELECT
F
UNCTION
T
ABLE
Inputs
OEA
0
1
Outputs
QA0/nQA0
Hi-Z
Active
T
ABLE
3G. OEB S
ELECT
F
UNCTION
T
ABLE
Inputs
OEB
0
1
Outputs
QB0/nQB0, QB1/nQB1
Hi-Z
Active
IDT
™
/ ICS
™
LVDS FREQUENCY SYNTHESIZER
4
ICS844003CG-01 REV A OCTOBER 31, 2006
ICS844003-01
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PRELIMINARY
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
70°C/W (0 mps)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO_A
= V
DDO_B
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO_A,
V
DDO_B
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current; NOTE 1
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
115
9
46
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
NOTE 1: Only one output bank enabled for 85°C operation.
Microchip MCU
