FemtoClock
®
Crystal/LVCMOS-to-
LVDS/LVCMOS Frequency Synthesizer
ICS8440258-46
PRELIMINARY DATA SHEET
General Description
The ICS8440258-46 is an 8 output synthesizer optimized to
generate Ethernet clocks. Using a 25MHz, 18pF parallel resonant
crystal, the device will generate both 125MHz and 25MHz clocks
with mixed LVDS and LVCMOS/LVTTL output logic. The
ICS8440258-46 uses IDT’s 3
RD
generation low phase noise VCO
technology and can achieve <1ps typical rms phase jitter, easily
meeting Ethernet jitter requirements. The ICS8440258-46 is
packaged in a small, 5mm x 5mm VFQFN package.
Features
•
•
•
•
•
•
•
Four differential LVDS outputs at 125MHz
Two LVCMOS/LVTTL single-ended outputs at 125MHz
Two LVCMOS/LVTTL single-ended outputs at 25MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
VCO range: 490MHz - 680MHz
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.34ps (typical)
Full 2.5V supply mode
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
nXTAL_SEL
XTAL_OUT
REF_CLK
nPLL_SEL
XTAL_IN
V
DDA
V
DD
MR
32 31 30
Q0
nQ0
GND
Q1
nQ1
V
DD
Q2
nQ2
1
2
3
4
5
6
7
8
9
29 28
27 26 25
24
23
22
21
20
19
18
17
nc
nc
nc
GND
Q7
V
DDO2
Q6
GND
Block Diagram
MR
Pulldown
Q0
10 11 12 13 14 15 16
ICS8440258-46
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
K Package
Top View
V
DDO1
GND
GND
nQ3
V
DD
Q3
Q4
Q5
nPLL_SEL
Pulldown
nQ0
Q1
nQ1
25MHz
XTAL_IN
Q2
OSC
XTAL_OUT
REF_CLK
Pulldown
0
Phase
Detector
1
VCO
490-680MHz
1
÷5
0
nQ2
Q3
nQ3
Q4
nXTAL_SEL
Pulldown
÷25
Q5
Q6
Q7
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
ICS8440258AK-46 REVISION B NOVEMBER 22, 2010
1
©2010 Integrated Device Technology, Inc.
ICS8440258-46 Preliminary Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 2
3, 12,
16, 17, 21
4, 5
6, 11, 27
7, 8
9, 10
13, 15, 18, 20
14
19
22, 23, 24
25
26
Name
Q0, nQ0
GND
Q1, nQ1
V
DD
Q2, nQ2
Q3, nQ3
Q4, Q5, Q6, Q7
V
DDO1
V
DDO2
nc
V
DDA
nPLL_SEL
Output
Power
Output
Power
Output
Output
Output
Power
Power
Unused
Power
Input
Pulldown
Type
Description
Differential clock outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Core supply pins.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply pin for Q4 and Q5 LVCMOS outputs.
Output supply pin for Q6 and Q7 LVCMOS outputs.
No connect.
Analog supply pin.
PLL Bypass. When LOW, the output is driven from the VCO output. When
HIGH, the PLL is bypassed and the output frequency = reference clock
frequency/N output divider. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When logic LOW, the internal dividers
and the outputs are enabled. LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects between the crystal or REF_CLK inputs as the PLL reference
source. When HIGH, selects REF_CLK. When LOW, selects XTAL inputs.
LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the input.
28
29
30
31,
32
MR
REF_CLK
nXTAL_SEL
XTAL_OUT,
XTAL_IN
Input
Input
Input
Pulldown
Pulldown
Pulldown
Input
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
Output Impedance
Q[4:7]
V
DDO1,
V
DDO2
= 2.5V
V
DDO1,
V
DDO2
= 2.625V
Test Conditions
Minimum
Typical
4
8
51
22
Maximum
Units
pF
pF
k
Ω
Ω
ICS8440258AK-46 REVISION B NOVEMBER 22, 2010
2
©2010 Integrated Device Technology, Inc.
ICS8440258-46 Preliminary Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Operating Temperature Range, T
A
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDOx
+ 0.5V
10mA
15mA
0°C to +70°C
33.1°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDO1
= V
DDO2
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO1,
V
DDO2
I
DD
+ I
DDO1
+
I
DDO2
I
DDA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.13
2.375
Typical
2.5
2.5
2.5
170
13
Maximum
2.625
V
DD
2.625
Units
V
V
V
mA
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO1
= V
DDO2
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High
Voltage; NOTE 1
Output Low
Voltage; NOTE 1
nXTAL_SEL, MR,
REF_CLK, nPLL_SEL
nXTAL_SEL, MR,
REF_CLK, nPLL_SEL
Q[4:7]
Q[4:7]
V
DD
= V
IN
= 2.625V
V
DD
= 2.625V, V
IN
= 0V
V
DDO1,
V
DDO2
= 2.5V
±5%
V
DDO1,
V
DDO2
= 2.5V
±5%
-5
1.8
0.5
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
150
Units
V
V
µA
µA
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DDOX
/2. See Parameter Measurement Information,
Output Load Test Circuit diagram.
ICS8440258AK-46 REVISION B NOVEMBER 22, 2010
3
©2010 Integrated Device Technology, Inc.
ICS8440258-46 Preliminary Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 3C. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
390
50
1.25
50
Maximum
Units
mV
mV
V
mV
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance
Shunt Capacitance
Drive Level
Test Conditions
Minimum
Typical
Fundamental
25
50
7
1
MHz
Maximum
Units
Ω
pF
mW
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= V
DDO1
= V
DDO2
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
f
OUT
Parameter
Q[0:3], nQ[0:3]
Output Frequency
Q4, Q5
Q6, Q7
tsk(o)
Output Skew;
NOTE 2
RMS Phase Noise
Jitter (Random);
NOTE 3
Output
Rise/Fall Time
Output
Duty Cycle
Q[0:3], nQ[0:3];
NOTE 1A
Q[4:7]; NOTE 1B
Q[0:3], nQ[0:3]
Q4, Q5
Q[0:3], nQ[0:3]
Q[4:7]
Q[0:3], nQ[0:3]
Q[4:7]
125MHz, Integration Range:
1.875MHz - 20MHz
125MHz, Integration Range:
1.875MHz - 20MHz
20% to 80%
20% to 80%
Test Conditions
Minimum
Typical
125
125
25
50
50
0.34
0.37
480
1.4
50
50
Maximum
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
ns
%
%
tjit(Ø)
t
R
/ t
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1A: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 1B: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDOX
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Refer to Phase Noise Plots.
ICS8440258AK-46 REVISION B NOVEMBER 22, 2010
4
©2010 Integrated Device Technology, Inc.
ICS8440258-46 Preliminary Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Typical Phase Noise at 125MHz (LVCMOS)
125MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.37ps (typical)
Noise Power
dBc
Hz
Raw Phase Noise Data
Offset Frequency (Hz)
ICS8440258AK-46 REVISION B NOVEMBER 22, 2010
5
➝
Phase Noise Result by adding
an Ethernet filter to raw data
➝
Ethernet Filter
➝
©2010 Integrated Device Technology, Inc.
