LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-
TO-0.7V HCSL FANOUT BUFFER
ICS85102I
G
ENERAL
D
ESCRIPTION
The ICS85102I is a low skew, high performance 1-
to-2 Differential-to-HCSL fanout buffer and a mem-
HiPerClockS™
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from IDT. The ICS85102I
has a differential clock input. The CLK0, nCLK0
input pair can accept most standard differential input levels.
The clock enable is internally synchronized to eliminate runt
clock pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
F
EATURES
•
Two 0.7V differential HCSL outputs
•
Selectable differential CLK0, nCLK0 or LVCMOS inputs
•
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
•
CLK1 can accept the following input levels:
LVCMOS or LVTTL
•
Maximum output frequency: 500MHz
•
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
•
Output skew: 65ps (maximum)
•
Part-to-part skew: 600ps (maximum)
•
Propagation delay: 3.2ns (maximum)
•
Additive phase jitter, RMS: 0.14ps typical @ 250MHz
•
3.3V operating supply
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
Guaranteed output and par t-to-par t skew characteristics
make the ICS85102I ideal for those applications demanding
well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
Pullup
CLK0
Pulldown
nCLK0
Pullup/Pulldown
CLK1
Pulldown
CLK_SEL
Pulldown
IREF
D
Q
LE
0
Q0
nQ0
1
Q1
nQ1
P
IN
A
SSIGNMENT
CLK_EN
CLK_SEL
CLK0
nCLK0
CLK1
nc
nc
IREF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
V
DD
Q0
nQ0
Q1
nQ1
V
DD
V
DD
ICS85102I
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm body package
G Package
Top View
IDT
™
/ ICS
™
0.7V HCSL FANOUT BUFFER
1
ICS85102AGI REV. A JUNE 10, 2008
ICS85102I
LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
Name
CLK_EN
Input
Type
Description
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
Pullup
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVTTL / LVCMOS interface levels.
Clock select input. When HIGH, selects CLK1 input.
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVTTL / LVCMOS interface levels.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input.
Pulldown
Pulldown Single-ended clock input. LVTTL / LVCMOS interface levels.
No connect.
An external fixed resistor (475
Ω
) from this pin to ground provides a
reference current used for differential current-mode Qx/nQx clock outputs.
Positive supply pins.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Power supply ground.
internal input resistors. See Table 2, Pin Characteristics, for typical values.
2
3
4
5
6, 7
8
CLK_SEL
CLK0
nCLK0
CLK1
nc
IREF
Input
Input
Input
Unused
Input
Power
9, 10, 15
V
DD
11, 12
nQ1, Q1
Output
13, 14
nQ0, Q0
Output
16
GND
Power
NOTE:
Pullup
and
Pulldown
refer to
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT
™
/ ICS
™
0.7V HCSL FANOUT BUFFER
2
ICS85102AGI REV. A JUNE 10, 2008
ICS85102I
LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK0, nCLK0
CLK1
CLK0, nCLK0
CLK1
Q0:Q1
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Outputs
nQ0:nQ1
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
Disabled
Enabled
nCLK0
CLK0
CLK_EN
nQ0, nQ1
Q0, Q1
F
IGURE
1. CLK_EN T
IMING
D
IAGRAM
IDT
™
/ ICS
™
0.7V HCSL FANOUT BUFFER
3
ICS85102AGI REV. A JUNE 10, 2008
ICS85102I
LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
100.3°C/W (0 mps)
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 10%, T
A
= -40°C
TO
85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Unterminated
Test Conditions
Minimum
2.97
Typical
3.3
Maximum
3.63
27
Units
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 10%, T
A
= -40°C
TO
85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input
High Current
Input
Low Current
CLK1, CLK_SEL
CLK_EN
CLK1, CLK_SEL
CLK_EN
V
IN
= V
DD
= 3.63V
V
IN
= V
DD
= 3.63V
V
IN
= 0V, V
DD
= 3.63V
V
IN
= 0V, V
DD
= 3.63V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V ± 10%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK0/nCLK0
CLK0
nCLK0
Test Conditions
V
DD
= V
IN
= 3.63V
V
DD
= 3.63V, V
IN
= 0V
V
DD
= 3.63V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
Peak-to-Peak Input Voltage; NOTE 1
Common Mode Input Voltage;
V
CMR
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
IDT
™
/ ICS
™
0.7V HCSL FANOUT BUFFER
4
ICS85102AGI REV. A JUNE 10, 2008
ICS85102I
LOW SKEW, 1-TO-2, DIFFERENTIAL/LVCMOS-TO-0.7V HCSL FANOUT BUFFER
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 10%, T
A
= -40°C
TO
85°C
Symbol Parameter
f
MAX
t
PD
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Absolute Maximum Output Voltage;
NOTE 5, 10
Absolute Minimum Output Voltage;
NOTE 5, 11
Ringback Voltage; NOTE 6, 13
Time before V
RB
is allowed; NOTE 6, 13
Absolute Crossing Voltage; NOTE 5, 8, 9
Total Variation of V
CROSS
over all edges;
NOTE 5, 8, 12
Rise/Fall Edge Rate; NOTE 6, 7
Measured between
-150mV to +150mV
100MHz (12kHz - 20MHz)
250MHz (12kHz - 20MHz)
0.22
0.14
1150
-300
-100
500
250
550
140
0.6
5.5
100
Test Conditions
CLK_SEL = 0
CLK_SEL = 1
CLK_SEL = 0
CLK_SEL = 1
2.0
2.0
Minimum
Typical
Maximum
500
250
3.2
2.8
65
600
Units
MHz
MHz
ns
ns
ps
ps
ps
ps
mV
mV
V
ps
mV
mV
V/ns
t
sk(o)
t
sk(pp)
t
jit
V
MAX
V
MIN
V
RB
t
STABLE
V
CROSS
ΔV
CROSS
Output Duty Cycle; NOTE 14
45
55
%
odc
All parameters measured at IJ 250MHz unless noted otherwise.
NOTE 1: Measured from the V
DD
/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output
differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Measurement taken from single-ended waveform.
NOTE 6: Measurement taken from differential waveform.
NOTE 7: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be
monotonic through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential
zero crossing. See Parameter Measurement Information Section.
NOTE 8: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 9: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all
crossing points for this measurement. See Parameter Measurement Information Section.
NOTE 10: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 11: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of Rising Qx and Falling nQx. This is the maximum allowed variance
in the V
CROSS
for any par ticular system. See Parameter Measurement Information Section.
NOTE: 13. T
STABLE
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges
before it is allowed to droop back into the V
RB
±100mV differential range. See Parameter Measurement Information Section.
NOTE 14: Input duty cycle must be 50%.
IDT
™
/ ICS
™
0.7V HCSL FANOUT BUFFER
5
ICS85102AGI REV. A JUNE 10, 2008
