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PRELIMINARY

DIFFERENTIAL TRANSLATOR/REPEATER

ICS854S44I

ENERAL

ESCRIPTION

T h e I C S 8 5 4S44I i s a high performance Dif-

ferential-to-LVDS Translator a n d a m e m b e r o f

HiPerClockS™

t h e H i Pe r C l o c k S ™ f a m i l y o f H i g h Pe r f o r -

m a n c e C l o ck S o l u t i o n s f r o m I DT. The PCLKx,

nPCLKx pairs can accept most standard differ-

ential input levels. T h e I C S 8 5 4S44I i s c h a r a c t e r i z e d t o

o p e r a t e f r o m a 3 . 3 V p ow e r s u p p l y.

EATURES

•

Four differential LVDS output banks

•

Four differential clock input pairs

•

PCLKx, nPCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, CML, SSTL

•

Maximum output frequency: 1.5GHz

•

Translates any single ended input signal to LVDS levels

with resistor bias on nCLKx input

PPLICATIONS

•

622MHz central office clock distribution

•

High speed network routing

•

Wireless basestations

•

Low jitter clock repeater

•

Serdes LVPECL output to FPGA LVDS input translator

•

AMC clock driver for ATCA systems

•

Propagation delay: 480ps (typical)

•

Additive phase jitter, RMS: 0.13ps (typical)

•

Full 3.3V power supply

•

-40°C to 85°C ambient operating temperature

•

Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

LOCK

IAGRAM

OE0

PCLK0

nPCLK0

OE1

PCLK1

nPCLK1

OE2

PCLK2

nPCLK2

OE3

PCLK3

nPCLK3

Pullup

Pulldown

Pullup/Pulldown

Pullup

Pulldown

Pullup/Pulldown

Pullup

Pulldown

Pullup/Pulldown

Pullup

Pulldown

Pullup/Pulldown

SSIGNMENT

nQ0

nPCLK0

PCLK0

GND

nQ0

OE0

OE1

nQ1

PCLK1

nPCLK1

nPCLK3

PCLK3

nQ3

OE3

OE2

nQ2

GND

PCLK2

nPCLK2

nQ1

nQ2

nQ3

ICS854S44I

28-Lead TSSOP

4.4mm x 9.7mm x 0.925mm package body

G Package

Top View

The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization

and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.

IDT

™

/ ICS

™

DIFFERENTIAL TRANSLATOR/REPEATER

ICS854S44AGI REV. A APRIL 5, 2007

ICS854S44I

DIFFERENTIAL TRANSLATOR/REPEATER

PRELIMINARY

ABLE

1. P

ESCRIPTIONS

Number

4, 18

5, 6

7, 8,

21, 22

9, 10

11, 25

14, 15, 28

19, 20

23, 24

Name

nPCLK0

PCLK0

GND

Q0, nQ0

OE0, OE1,

OE2, OE3

nQ1, Q1

PCLK1

nPCLK1

nPCLK2

PCLK2

Q2, nQ2

nQ3, Q3

PCLK3

Type

Output

Input

Power

Output

Input

Output

Power

Input

Unused

Input

Output

Input

Pullup

Description

Bias voltage.

Pullup/

Inver ting differential clock input. V

/2 default when left floating.

Pulldown

Pulldown Non-inver ting differential clock input.

Power supply ground

Differential output pair. LVPECL interface levels.

Active high output enable. When logic HIGH, the output pair is enabled.

When logic LOW, the output pair is in a high impedance state. The OEx

pins have an internal pullup resistor so the default power-up state of the

outputs are enabled. LVCMOS/LVTTL interface levels.

Differential output pair. LVPECL interface levels.

Power supply pins.

Pulldown Non-inver ting differential clock input.

Pullup/

Inver ting differential clock input. V

/2 default when left floating.

Pulldown

No connect.

Pullup/

Inver ting differential clock input. V

/2 default when left floating.

Pulldown

Pulldown Non-inver ting differential clock input.

Differential output pair. LVPECL interface levels.

Pulldown Non-inver ting differential clock input.

Pullup/

Inver ting differential clock input. V

/2 default when left floating.

nPCLK3

Input

Pulldown

NOTE:

Pullup

and

Pulldown

refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

ABLE

2. P

HARACTERISTICS

Symbol

PULLUP

PULLDOWN

Parameter

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

Test Conditions

Minimum

Typical

Maximum

Units

kΩ

IDT

™

/ ICS

™

DIFFERENTIAL TRANSLATOR/REPEATER

ICS854S44AGI REV. A APRIL 5, 2007

ICS854S44I

DIFFERENTIAL TRANSLATOR/REPEATER

PRELIMINARY

BSOLUTE

AXIMUM

ATINGS

Supply Voltage, V

Inputs, V

Outputs, V

4.6V

-0.5V to V

+ 0.5V

-0.5V to V

+ 0.5V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause per manent damage to the

device. These ratings are stress specifications only. Functional op-

eration of product at these conditions or any conditions beyond

those listed in the

DC Characteristics

AC Characteristics

is not

implied. Exposure to absolute maximum rating conditions for ex-

tended periods may affect product reliability.

Package Thermal Impedance,

77.1°C/W (0 lfpm)

Storage Temperature, T

STG

-65°C to 150°C

ABLE

3A. P

OWER

UPPLY

DC C

HARACTERISTICS

= 3.3V±5%, T

= -40°C

85°C

Symbol

Parameter

Core Supply Voltage

Power Supply Current

Test Conditions

Minimum

3.135

Typical

3. 3

105

Maximum

3.465

Units

ABLE

3B. LVCMOS / LVTTL DC C

HARACTERISTICS

= 3.3V±5%, T

= -40°C

85°C

Symbol

Parameter

Input High Voltage

Input Low Voltage

Input High Current

Input Low Current

OE0:OE3

= V

= 3.465V

= 3.465V, V

= 0V

-150

Test Conditions

Minimum Typical

-0.3

Maximum

+ 0.3

0.8

Units

µA

ABLE

3C. D

IFFERENTIAL

LVPECL DC C

HARACTERISTICS

= 3.3V±5%, T

= -40°C

85°C

Symbol

CMR

Parameter

Input High Current

Input Low Current

PCLK[0:3],

nPCLK[0:3]

PCLK[0:3]

nPCLK[0:3]

Test Conditions

= V

= 3.465V

= 3.465V, V

= 0V

= 3.465V, V

= 0V

-5

-150

0.3

GND + 1.5

Minimum

Typical

Maximum

150

Units

µA

Peak-to-Peak Input Voltage

Common Mode Input Voltage; NOTE 1, 2

Bias Voltage

NOTE 1: Common mode voltage is defined as V

NOTE 2: For single ended applications, the maximum input voltage for PCLKx and nPCLKx is V

+ 0.3V.

ABLE

3D. LVDS DC C

HARACTERISTICS

= 3.3V±5%, T

= -40°C

85°C

Symbol

Parameter

Differential Output Voltage

Magnitude Change

Offset Voltage

Magnitude Change

Test Conditions

Minimum

Typical

360

1.18

Maximum

Units

NOTE: Please refer to Parameter Measurement Information for output information.

IDT

™

/ ICS

™

DIFFERENTIAL TRANSLATOR/REPEATER

ICS854S44AGI REV. A APRIL 5, 2007

ICS854S44I

DIFFERENTIAL TRANSLATOR/REPEATER

PRELIMINARY

ABLE

4. AC C

HARACTERISTICS

= 3.3V ± 5%, T

= -40°C

85°C

Symbol Parameter

MAX

jit

/ t

Output Frequency

Propagation Delay; NOTE 1

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

Output Rise/Fall Time

Test Conditions

≥

200mV

480

200MHz, Integration Range:

12kHz - 20MHz

20% to 80%

0.13

160

Minimum

Typical

Maximum

1.5

Units

GHz

odc

Output Duty Cycle

All parameters measured at 500MHz unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

IDT

™

/ ICS

™

DIFFERENTIAL TRANSLATOR/REPEATER

ICS854S44AGI REV. A APRIL 5, 2007

ICS854S44I

DIFFERENTIAL TRANSLATOR/REPEATER

PRELIMINARY

ARAMETER

EASUREMENT

NFORMATION

SCOPE

3.3V±5%

POWER SUPPLY

+ Float GND –

nPCLK0: nPCLK3

Cross Points

CMR

LVDS

nQx

PCLK0:PCLK3

GND

UTPUT

OAD

AC T

EST

IRCUIT

nPCLK0: nPCLK3

PCLK0:PCLK3

nQ0:nQ3

Q0:nQ3

IFFERENTIAL

NPUT

EVEL

nQ0: nQ3

Q0:Q3

PERIOD

odc =

PERIOD

x 100%

ROPAGATION

ELAY

UTPUT

UTY

YCLE

ULSE

IDTH

ERIOD

Clock

Outputs

20%

DC Input

LVDS

100

/Δ V

out

➤

UTPUT

ISE

ALL

IME

out

DC Input

IFFERENTIAL

UTPUT

OLTAGE

ETUP

out

➤

/Δ V

FFSET

OLTAGE

ETUP

IDT

™

/ ICS

™

DIFFERENTIAL TRANSLATOR/REPEATER

➤

LVDS

➤

ICS854S44AGI REV. A APRIL 5, 2007

➤

80%

out

➤

参数对比

与ICS854S44AGI相近的元器件有：ICS854S44AGILFT、ICS854S44AGILF、ICS854S44AGIT。描述及对比如下：

型号	ICS854S44AGI	ICS854S44AGILFT	ICS854S44AGILF	ICS854S44AGIT
描述	Low Skew Clock Driver, 854S Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 X 9.70 MM, 0.925 MM HEIGHT, MO-153, TSSOP-28	Low Skew Clock Driver, 854S Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 X 9.70 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-28	Low Skew Clock Driver, 854S Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 X 9.70 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-28	Low Skew Clock Driver, 854S Series, 4 True Output(s), 0 Inverted Output(s), PDSO28, 4.40 X 9.70 MM, 0.925 MM HEIGHT, MO-153, TSSOP-28
是否无铅	含铅	不含铅	不含铅	含铅
是否Rohs认证	不符合	符合	符合	不符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
零件包装代码	TSSOP	TSSOP	TSSOP	TSSOP
包装说明	TSSOP,	TSSOP,	TSSOP,	TSSOP,
针数	28	28	28	28
Reach Compliance Code	not_compliant	compliant	compliant	not_compliant
系列	854S	854S	854S	854S
输入调节	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL	DIFFERENTIAL
JESD-30 代码	R-PDSO-G28	R-PDSO-G28	R-PDSO-G28	R-PDSO-G28
JESD-609代码	e0	e3	e3	e0
长度	9.7 mm	9.7 mm	9.7 mm	9.7 mm
逻辑集成电路类型	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
湿度敏感等级	1	3	3	1
功能数量	1	1	1	1
端子数量	28	28	28	28
实输出次数	4	4	4	4
最高工作温度	85 °C	85 °C	85 °C	85 °C
最低工作温度	-40 °C	-40 °C	-40 °C	-40 °C
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSSOP	TSSOP	TSSOP	TSSOP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）	240	260	260	240
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm
最大供电电压 (Vsup)	3.465 V	3.465 V	3.465 V	3.465 V
最小供电电压 (Vsup)	3.135 V	3.135 V	3.135 V	3.135 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES
温度等级	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
端子面层	TIN LEAD	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	TIN LEAD
端子形式	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	20	30	30	20
宽度	4.4 mm	4.4 mm	4.4 mm	4.4 mm