Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
LVCMOS/ LVTTL C
LOCK
G
ENERATOR W
/P
OLARITY
C
ONTROL
F
EATURES
• 20 LVCMOS/LVTTL outputs, 7Ω typical output impedance
• 1 LVCMOS/LVTTL clock input
• Maximum output frequency: 250MHz
• Selectable inverting and non-inverting outputs
• Bank enable logic allows unused banks to be
disabled in reduced fanout applications
• Output skew: 300ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Bank skew: 250ps (maximum)
• Multiple frequency skew: 350ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating supply
• -40°C to 85°C ambient operating temperature
ICS8701I-01
G
ENERAL
D
ESCRIPTION
The ICS8701I-01 is a low skew,
÷1, ÷2
LVCMOS/
LVTTL Clock Generator and a member of the
HiPerClockS™
HiPerClockS™family of High Performance Clock
Solutions from ICS. The low impedance LVCMOS
outputs are designed to drive 50Ω series or paral-
lel terminated transmission lines. The effective fanout can be
increased from 20 to 40 by utilizing the ability of the outputs to
drive two series terminated lines.
ICS
The divide select inputs, DIV_SELx, control the output frequency
of each bank. The outputs can be utilized in the ÷1, ÷2 or a
combination of ÷1 and ÷2 modes. The master reset/output en-
able input, nMR/OE, resets the internal dividers and controls
the active and high impedance states of all outputs. The output
polarity inputs, INV0:1, control the polarity (inverting or non-in-
verting) of the outputs of each bank. Outputs QA0:QA4 are in-
verting for every combination of the INV0:1 input. The timing
relationship between the inverting and non-inverting outputs at
different frequencies is shown in the Timing Diagrams.
The ICS8701I-01 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output and part-to-part skew characteristics make the
ICS8701I-01 ideal for those clock distribution applications de-
manding well defined performance and repeatability.
B
LOCK
D
IAGRAM
÷1
1
0
P
IN
A
SSIGNMENT
GND
QB2
GND
QB3
V
DDOB
QB4
QC0
V
DDOC
QC1
GND
QC2
GND
CLK
DIV_SELA
÷2
QA0:QA4
QC3
V
DDOC
QC4
QD0
V
DDOD
QD1
GND
QD2
GND
QD3
V
DDOD
QD4
1
0
QB0:QB4
DIV_SELB
1
0
QC0:QC4
DIV_SELC
1
0
QD0:QD4
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8701I-01
QB1
V
DDOB
QB0
QA4
V
DDOA
QA3
GND
QA2
GND
QA1
V
DDOA
QA0
DIV_SELD
nMR/OE
INV0
INV1
Output
Polarity
Control
48-Pin LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. A MARCH 4, 2004
DIV_SELA
DIV_SELB
CLK
GND
V
DD
INV0
GND
INV1
V
DD
nMR/OE
DIV_SELC
DIV_SELD
8701AYI-01
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
LVCMOS/ LVTTL C
LOCK
G
ENERATOR W
/P
OLARITY
C
ONTROL
Type
Output
Power
Output
Power
Power
Input
Input
Input
Power
Input
Input
Input
Input
Output
Power
Output
Power
Description
Bank C outputs. LVCMOS interface levels. 7
Ω
typical output impedance.
Output Bank C supply pins.
Bank D outputs. LVCMOS interface levels. 7
Ω
typical output impedance.
Output Bank D supply pins.
Power supply ground.
Pullup Controls frequency division for Bank D outputs. LVCMOS interface levels.
Pullup Controls frequency division for Bank C outputs. LVCMOS interface levels.
Master Reset and output enable. When HIGH, output drivers are
Pullup enabled. When LOW, output drivers are in HiZ and dividers are reset.
LVCMOS interface levels.
Core supply pins.
Pullup Determines polarity of outputs by banks. LVCMOS interface levels.
Pullup LVCMOS clock input.
Pullup Controls frequency division for Bank B outputs. LVCMOS interface levels.
Pullup Controls frequency division for Bank A outputs. LVCMOS interface levels.
Bank A outputs. LVCMOS interface levels. 7
Ω
typical output impedance.
Output Bank A supply pins.
Bank B outputs. LVCMOS interface levels. 7
Ω
typical output impedance.
Output Bank B supply pins.
ICS8701I-01
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 3,
43, 45, 47
2, 44
4, 6,
8, 10, 12
5, 11
7, 9, 18,
21, 28,
30, 37,
39, 46, 48
13
14
15
1 6, 20
17, 19
22
23
24
25, 27,
29, 31, 33
26, 32
34, 36,
38, 40, 42
35, 41
Name
QC3, QC4,
QC0, QC1, QC2
V
DDOC
QD0, QD1,
QD2, QD3, QD4
V
DDOD
GND
DIV_SELD
DIV_SELC
nMR/OE
V
DD
INV1, INV0
CLK
DIV_SELB
DIV_SELA
QA0, QA1,
QA2, QA3, QA4
V
DDOA
QB0, QB1,
QB2, QB3, QB4
V
DDOB
NOTE:
Pullup
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol Parameter
C
IN
R
PULLUP
C
PD
R
OUT
Input Capacitance
Input Pullup Resistor
Power Dissipation Capacitance (per output)
Output Impedance
V
DD
, *V
DDOx
= 3.465
5
7
Test Conditions
Minimum
Typical
4
51
15
12
Maximum
Units
pF
KΩ
pF
Ω
*
NOTE: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, and V
DDOD
.
T
ABLE
3. F
UNCTION
T
ABLE
nMR/OE
0
1
1
1
1
1
1
1
1
8701AYI-01
Inputs
DIV_SELx
INV1
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
INV0
X
0
1
0
1
0
1
0
1
Bank A
Hi Z
Inver ting
Inver ting
Inver ting
Inver ting
Inver ting
Inver ting
Inver ting
Inver ting
Bank B
Hi Z
Non-inver ting
Inver ting
Inver ting
Inver ting
Non-inver ting
Inver ting
Inver ting
Inver ting
Outputs
Bank C
Hi Z
Non-inver ting
Non-inver ting
Inver ting
Inver ting
Non-inver ting
Non-inver ting
Inver ting
Inver ting
Bank D
Hi Z
Non-inver ting
Non-inver ting
Non-inver ting
Inver ting
Non-inver ting
Non-inver ting
Non-inver ting
Inver ting
Qx Frequency
zero
fIN/2
fIN/2
fIN/2
fIN/2
fIN
fIN
fIN
fIN
REV. A MARCH 4, 2004
www.icst.com/products/hiperclocks.html
2
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
LVCMOS/ LVTTL C
LOCK
G
ENERATOR W
/P
OLARITY
C
ONTROL
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
ICS8701I-01
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
X
Symbol
V
DD
V
DDOx
Parameter
Core Supply Voltage
Output Supply Voltage; NOTE 1
Test Conditions
Minimum
3.135
3.135
2.375
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
95
32
Units
V
V
V
mA
mA
I
DD
Power Supply Current
Output Supply Current
I
DDOx
NOTE 1: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, and V
DDOD
.
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
X
Symbol Parameter
V
IH
Input High Voltage
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
INV0, INV1, nMR/OE
CLK
DIV_SELA, DIV_SELB,
DIV_SELC, DIV_SELD,
INV0, INV1, nMR/OE
CLK
Test Conditions
Minimum
2
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
5
Units
V
V
V
V
µA
µA
V
V
V
IL
Input Low Voltage
I
IH
I
IL
V
OH
Input High Current
Input Low Current
Output High Voltage; NOTE 1
V
DD
= V
IN
= 3.465V,
V
DD
= V
IN
= 2.625V
V
DD
= 3.465V, V
IN
= 0V,
V
DD
= 2.625V, V
IN
= 0V
*V
DDOx
= 3.465V
*V
DDOx
= 2.625V
-150
2.6
1.8
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DDOx
/2. See Parameter Measurement Information section,
"3.3V Output Load Test Circuit".
*NOTE: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, V
DDOD
.
0.5
V
8701AYI-01
www.icst.com/products/hiperclocks.html
3
REV. A MARCH 4, 2004
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
LVCMOS/ LVTTL C
LOCK
G
ENERATOR W
/P
OLARITY
C
ONTROL
X
ICS8701I-01
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
Output Frequency
f
MAX
t
PD
Propagation Delay; NOTE 1
Bank Skew; NOTE 2, 7
Output Skew; NOTE 3, 7
Multiple Frequency Skew; NOTE 4, 7
Par t to Par t Skew; NOTE 5, 7
Output Rise/Fall Time; NOTE 6
Output Duty Cycle
Output Enable Time; NOTE 6
20% to 80%
f
≤
133MHz
f > 133MHz
150
46
42
Measured on the
Falling Edge
Measured on the
Falling Edge
Test Conditions
Minimum
2.0
Typical
Maximum
250
3.5
250
300
350
700
800
54
58
6
Units
MHz
ns
ps
ps
ps
ps
ps
%
%
ns
ns
t
sk(b)
t
sk(o)
t
sk(w)
t
sk(pp)
t
R
/ t
F
odc
t
EN
t
DIS
Output Disable Time; NOTE 6
6
NOTE 1: Measured from the V
DD
/2 of the input to V
DDOx
/2 of the output.
NOTE 2: Defined as skew within a bank with equal load conditions.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOx
/2.
NOTE 4: Defined as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at V
DDOx
/2.
NOTE 5: Defined as skew between outputs on different devices operating a the same supply voltages and with equal
load conditions. Using the same type of input on each device, the output is measured at V
DDOx
/2.
NOTE 6: These parameters are guaranteed by characterization. Not tested in production.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= -40°C
TO
85°C
X
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
t
sk(inv) Inver ting Skew; NOTE 1, 2
f = 66.7MHz
400
NOTE 1: Defined as skew across banks of outputs switching in opposite directions operating at the same frequency
with the same supply voltages and equal load conditions. Measured at V
DDOx
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
Units
ps
8701AYI-01
www.icst.com/products/hiperclocks.html
4
REV. A MARCH 4, 2004
Integrated
Circuit
Systems, Inc.
L
OW
S
KEW
,
÷1, ÷2
LVCMOS/ LVTTL C
LOCK
G
ENERATOR W
/P
OLARITY
C
ONTROL
ICS8701I-01
P
ARAMETER
M
EASUREMENT
I
NFORMATION
1.65V ± 5%
2.05V ± 5% 1.25V ± 5%
V
DD
,
V
DDOx
SCOPE
Qx
V
DD
V
DDOx
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
V
DDO
2
-1.65V ± 5%
-1.25V ± 5%
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
PART 1
Qx
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
Qx
V
V
DDOx
2
V
DDOx
2
tsk(o)
DDOx
2
PART 2
Qy
Qy
V
DDOx
2
Qy
t
sk(pp)
V
DDOx
2
tsk(ω)
P
ART
-
TO
-P
ART
S
KEW
V
QAx, QBx,
QCx, QDx
DDOX
O
UTPUT
S
KEW
& M
ULTIPLE
F
REQUENCY
S
KEW
2
Pulse Width
t
PERIOD
80%
20%
t
R
80%
20%
t
F
Clock
Outputs
odc =
t
PW
t
PERIOD
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
O
UTPUT
R
ISE
/F
ALL
T
IME
CLK
QAx,QBx,
QCx, QDx
V
DD
2
V
DDOx
2
t
PD
V
CLK
V
Qx
Qy
DD
2
DDOx
2
V
DDOx
2
t
sk(in)
P
ROPAGATION
D
ELAY
8701AYI-01
I
NVERTING
S
KEW
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5
REV. A MARCH 4, 2004
